Folded Cascode Operational Amplifier Research Articles

An ultra-low power adjustable current-mode analog integrated general purpose artificial neural network classifier

This study introduces a methodology tailored to analog hardware architecture for implementing an artificial neural network. The fundamental components of the architecture include current-mode circuits, representing the class, and a voltage-mode comparator. Specifically, the current mode circuits comprise the Mahalanobis distance circuit, Sigmoid function circuit, analog multiplier, and current mirrors. Regarding the voltage comparator, which receives the final decision, a folded-cascode operational amplifier is employed. The operational principles of the architecture are extensively explained and applied in a power-efficient configuration (operating under 976nW) with low power supply rails (0.6 V). The proposed implementation is tested on real-world biomedical classification tasks, achieving classification accuracy exceeding 91.6%. The designs are implemented using a 90nm CMOS process and developed using the Cadence IC Suite for both schematic and layout design. Monte-Carlo analysis, encompassing both process and mismatch, as well as corner analysis, are provided to confirm the robust characteristics of the proposed classifier. Through comparative analysis of post-layout simulation results with an equivalent software-based classifier and related literature, the proper operation of the proposed architecture is confirmed.

Design and simulation of a bioimpedance detection analog front-end targeting medical applications

This paper presents the design of a bio-impedance detection analog front-end system, which is critical for continuous monitoring of physiological signals in the prevention and treatment of diseases such as coronary heart disease in the context of an aging population. The analog front-end system employs a capacitive-coupled chopper instrumentation amplifier with a fully differentially folded cascode operational amplifier as the core amplifier, and a common-mode feedback loop is introduced to improve the common-mode rejection ratio due to the high requirement for noise suppression. The power supply voltage of the design is 3.3V, achieving a total current consumption of 45uA and a total power consumption of 0.15mW. The core operational amplifier provides a maximum open-loop gain of 58 dB and a -3dB bandwidth of 8.2KHz. The power supply rejection ratio for the positive supply and ground achieved values of 102dB and 108dB, respectively. The common-mode rejection ratio of the chopper instrumentation amplifier can reach 109 dB, which is critical for suppressing common-mode noise.

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

An NMOS transistor-based high-gain operational amplifier designed in 0.25-micron CMOS technology

This project describes in detail the process of designing and simulating at first a one stage folded cascode operational amplifier using 0.25 um CMOS Technology with the self-biasing scheme for the NMOS differential input stage is discussed here. The design of the required circuits is done using the LTspice simulator. We will see that the simulation results approximately matches with the desired and theoretically calculated performance values. We are changing width values to bring all the transistors of the circuit in saturation. Then two Stage Folded Cascode Operational Amplifier with Miller compensation technique for the NMOS input. The operational amplifiers circuit is designed with 0.25 µm CMOS Technology using LTspice software. The applied methodology to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like DC Gain and Phase Margin (PM) are presented and discussed. Finally, we have got after performance analysis that designed circuit based on NMOS input provide a 96 DC Gain.

Folded Cascode Operational Amplifier Design Utilizing 0.25 µm CMOS Technology

A one-stage Folded Cascode Operational Amplifier with the self-biasing scheme for the PMOS differential input stage is designed by using LTspice simulator and the designing procedure is described. This folded op amp will have a high Common-mode input range (ICMR) and a high maximum voltage output thereby high gain. The LTspice simulation results correlate very well with the hand calculations obtained theoretical values. All the MOSFETs are kept in saturation to ensure high open loop gain. Then, a two-stage op amp circuit has been designed by assuming Zero (z)= 10 GB, and phase margin (PM= 68o). The obtained result of the output gain for this design was Avo= 91 dB, indicating that the design has a high gain.

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

A Time-Interleaved Charge Pump Internal Power Supply Generation Circuit

A charge pump internal power supply generation circuit for rail-to-rail operational amplifier is proposed, which combines a non-overlapping clock signal and a time-interleaved boost charge pump to achieve an internal power supply which is higher than the power supply voltage. A voltage follower is used to avoid glitch during time-interleaving switching. The charge pump internal power supply circuit is realized by 0.5μm CMOS process. The simulation results show that the internal power supply circuit of the charge pump can generate an internal power supply signal which is 1.8V higher than the power supply voltage. After applying this internal power supply to the PMOS input folded cascode operational amplifier, the operational amplifier achieves the rail-to-rail input, and the unity gain bandwidth and phase margin are stable.

Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

Design procedure for noise and power optimisation of CMOS folded-cascode operational transconductance amplifier based on the inversion coefficient

A Hybrid-Mode LDO Regulator with Fast Transient Response Performance for IoT applications

A hybrid-mode low-drop out (LDO) voltage regulator with fast transient response performance for IoT applications is proposed in this paper. The proposed LDO regulator consist of two sections. First section is an analog regulator which includes a folded cascode operational amplifier to achieve good PSRR. Second section is current DAC and detectors whitch includes a cource current DAC, sink current DAC, undershoot detectors, and overshoot detectors. The current DAC and detectors are designed to obtain a low drop out and fast transient response. The proposed hybrid-mode LDO voltage regulator has been designed, simulated and layouted in Cadence using TSMC 90 nm CMOS technology. The input range of the LDO regulator is 1.2–2.0 V, and it can produces an output voltage of 1.2V. The LDO regulator achieves 58uA quiescent current, -69 PSRR @ 1 KHz noise frequency and an output voltage drop of around 60mV for a load current step of 100 mA. The final design occupies approximately 0.09 mm2.

Design of folded cascode op amp and its application – bandgap reference circuit

PurposeReference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.Design/methodology/approachThis paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.FindingsThe post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.Research limitations/implicationsSlew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.Practical implicationsReference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.Social implicationsBGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.Originality/valueFC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Design of a Fully Differential CMOS OTA Folded Cascode for Modulation

In this paper, the design and experimental results of a fully-differential folded-cascode operational amplifier of transconductance (OTA) is presented. This active circuit is for the use in a  low-pass modulator. The structure of the OTA is for obtaining a transition frequency of 1.0GHz. From the circuit synthesis, the OTA can handle the signals with the peak-to-peak amplitude of 300mV, and consumes 1.5mA from 1.2V supply. The OTA is fabricated in 130nm standard CMOS technology.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

PurposeThe purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application.Design/methodology/approachAn op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2.FindingsMeasured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V.Originality/valueThe experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

An evolutionary-based design methodology for performance enhancement of a folded-cascode OTA using symbiotic organisms search algorithm and gm/ID technique

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This algorithm is quite useful in solving optimization problems but it suffers from higher computational time. Thus in order to minimize the computational time along with SOS algorithm, gm/ID design methodology is used. The proposed method not only guarantees appropriate bias conditions but also estimates the reduced search spaces for the design variables of the MOSFETs. To analyse the performance of SOS algorithm along with gm/ID design methodology, a low noise differential folded-cascode operational transconductance amplifier has been designed and verified using Cadence Spectre circuit simulator in UMC 0.18 µm CMOS process and MATLAB. From the optimisation results, it is observed that the gm/ID method combined with SOS algorithm converges earlier than SOS alone. The total computational time of simulation obtained using the proposed method is 8.59 s while errors found are less than 8%. Hence, this method not only reduces computational time but also improves the accuracy of the circuit design.

CMOS Plasmon Detector With Three Different Body-Biasing MOSFETs

A complementary metal–oxide–semiconductor (CMOS) plasmon detector using metal–oxide–semiconductor field–effect transistors (MOSFETs) biased at three different body voltages is proposed for high sensitivity and a wide dynamic range. The detection core consists of three differential MOSFET detectors biased at different body voltages based on the photoresponse variation depending on the body potential. The sensitivity of the proposed detector is improved through an increase in the nonlinearity owing to the uses of transistors biased by negative body voltages, and the dynamic range of the detector is widened through the parallel-connected detectors individually biased at different body voltages. A 200-GHz signal is simultaneously incident to the detection cores configured in-parallel through the integrated differential antenna, and DC voltages converted using the different photoresponsivity of the cores are current-combined at the preamplifier and amplified with a three-stage folded-cascode operational amplifier. Simulation and measurement results of the proposed detector designed using TSMC 0.25- $\mu \text{m}$ CMOS technology show that the negative body-biasing (set to 0, −0.2, and −0.4 V), in the MOSFET can improve the voltage responsivity of 2.63 times, the sensitivity by 2.9-fold compared to zero body-biasing, reaching a dynamic range of 11.1% in the CMOS plasmon detector. Raster-scanned imaging for 60- $\mu \text{m}$ thick copper tapes with a line width of 6–12 mm attached to 10-mm thick Styrofoam demonstrates that the signal-to-noise ratio of 200-GHz images can be improved from 25.5 dB to 30.6 dB when using the proposed detector with three different body-biased MOSFETs.

Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

Design of Low Power, High Gain Fully Differential Folded Cascode Operational Amplifier for Front End Read Out Circuits

The Front end read out circuits are major block in the implementation of Capacitive MEMS accelerometer. Front end read-out circuits comprises of preamplifier block containing folded cascode fully differential operational amplifier which are required for the signal conditioning of the signals received from the MEMS sensors. The op-amps are prime elements in design and implementation of mixed signal integrated circuits. The high gain and low power of the designed circuits helps in the designing of high precision IC’s for numerous application. Amongst the available topologies folded cascode topology plays vital role in the design and development of low power, high gain read out circuits. This paper illustrates the design and analysis of low power, high gain fully differential Folded Cascode Operational Amplifier for front end read out circuits. The designed op-amp exhibits a power consumption or dissipation of 92.14 μW and relatively higher open loop DC gain value with a value calculated at 81.33 dB by employing folded cascode topology. The UGB and Phase Margin for the selected design are 35 MHz and 83.60 respectively. The design operates at 5V power supply with the bias current of 12.11 μA. The circuit design and simulations have been implemented using 0.18 μm CMOS technology.

Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach

This article proposes an efficient approach to design two different CMOS analogue circuits, namely p-channel Metal-Oxide-Semiconductor (PMOS) driver-based two-stage comparator and n-channel Metal-Oxide-Semiconductor (NMOS) driver-based folded-cascode operational amplifier, using a modified version of particle swarm optimization (PSO) known as craziness-based PSO (CRPSO) algorithm. PSO replicates the behaviour of bird flocking, and it requires a fewer number of control parameters. The drawbacks of PSO are premature convergence and stagnation problem. Due to these drawbacks, the PSO is improved to CRPSO for the optimal design of analogue circuits. The near-global optimal solution has been achieved by using the CRPSO. The CRPSO is used to attain the optimal sizes of the MOS devices for the individual circuits, which lead to the minimization of the total MOS area occupied by the circuit. SPICE simulation has also been carried out with the optimal device dimensions achieved from the CRPSO algorithm. Statistical analysis and the process corner analysis have also been performed for the above mentioned circuits. SPICE-based results confirm that the CRPSO-based approach is a better technique compared to the other earlier reported methods for both the circuits.

Design and Comparative Analysis of Folded Cascode OP-AMP with Different Input Stages

The work done represents the overall structure and comparative analysis of folded cascode operational amplifier (op-amp) in fully differential configuration having PMOS and NMOS input stages with robust biasing and common mode feedback circuit under different process, voltage and temperature variations in 180nm technology with 1.8V power supply and 1pf load resulting in good optimization among the parameters such as gain, bandwidth, phase margin and power dissipation.

Design of a sub-1V CMOS reference voltage generator

In this paper a low complexity, sub-1V, reference voltage generator with low voltage sensitivity over PVT variation and high power supply rejection ratio (PSRR) is proposed. It consists of a traditional bandgap reference core where resistors are used for generating both the PTAT and CTAT currents, which are then added forming a temperature-independent current. A new 1 V modified folded cascode operational amplifier is proposed and used in the main bandgap’s loop resulting in low offset, high loop gain and adequate loop phase margin of 58.9°. The loop consists of only two inverting stages and the circuit can be integrated entirely without the need of external large capacitors for frequency compensation. A regulated cascode current source is employed for accurately mirroring of the core temperature-independent current to a resistive load, where the reference voltage is generated. The proposed circuit was simulated in SPECTRE achieving an output reference voltage variation of 3.62%, without trimming, over process variation corners with ±10% variation of the 1 V power supply voltage and within the industrial temperature range, from −40 °C to 125 °C. The temperature coefficient from −40 °C to 125 °C is 6.81 ppm/°C at 1 V at the typical process corner. The PSRR at 1 Hz and the output RMS noise within a bandwidth of 100 MHz are −69.85 dB and 279 μV RMS, respectively, at the typical process corner, at a supply voltage of 1 V and temperature of 27 °C. Typical power consumption is 452 μA at 1 V.