Floorplan Representation Research Articles

Design optimization of floor plan for public housing buildings in Hong Kong with consideration of natural ventilation, noise, and daylighting

Indoor environmental quality plays a crucial role in determining the overall quality of life. This study aims to develop a design optimization approach for the floor plan of public housing buildings with modular flat design in Hong Kong, with focus on enhancing natural ventilation, reducing noise levels, and improve daylighting conditions. The evaluation of these environmental factors was conducted using deep neural network models and a mathematically based Calculation of Road Traffic Noise model. A general floor plan representation was developed for three- and four-winged structures of public housing buildings. An optimization approach utilizing Bayesian optimization was applied to three studied cases: Hung Shing House, Hung Hei House, and Cheung Tai House. The optimization process resulted in an average 41.5 % improvement in average natural ventilation rate. The optimized building shapes effectively served as noise barriers, leading to an average reduction of 20 % in average noise levels. The existing window configurations of each unit type under the modular flat design already provided sufficient daylighting, resulting in only a minor improvement from the optimization process.

Unobtrusive Cognitive Assessment in Smart-Homes: Leveraging Visual Encoding and Synthetic Movement Traces Data Mining.

The ubiquity of sensors in smart-homes facilitates the support of independent living for older adults and enables cognitive assessment. Notably, there has been a growing interest in utilizing movement traces for identifying signs of cognitive impairment in recent years. In this study, we introduce an innovative approach to identify abnormal indoor movement patterns that may signal cognitive decline. This is achieved through the non-intrusive integration of smart-home sensors, including passive infrared sensors and sensors embedded in everyday objects. The methodology involves visualizing user locomotion traces and discerning interactions with objects on a floor plan representation of the smart-home, and employing different image descriptor features designed for image analysis tasks and synthetic minority oversampling techniques to enhance the methodology. This approach distinguishes itself by its flexibility in effortlessly incorporating additional features through sensor data. A comprehensive analysis, conducted with a substantial dataset obtained from a real smart-home, involving 99 seniors, including those with cognitive diseases, reveals the effectiveness of the proposed functional prototype of the system architecture. The results validate the system's efficacy in accurately discerning the cognitive status of seniors, achieving a macro-averaged F1-score of 72.22% for the two targeted categories: cognitively healthy and people with dementia. Furthermore, through experimental comparison, our system demonstrates superior performance compared with state-of-the-art methods.

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

Floor planning is indeed an obvious design process in VLSI physical layout since it specifies the dimensions, structure, as well as positions of components upon the chip; in addition, information regarding the overarching silicon area, interlinks, and latency is also provided. VLSI floor planning is an NP-hard issue as the floor plan representations are a crucial component in this process. The intricacy, as well as solution space of the floor plan layout, is influenced by the floorplan visualizations. To tackle the VLSI floor plan challenge, numerous researchers have developed numerous meta-heuristic optimization techniques. The main objective of this work presents a novel multi-objective hybrid optimization method for solving the floor plan optimization issue. Standard DOX and ALO are conceptually combined in the proposed hybrid optimization referred to as Dingo Updated Ant Lion Optimization (DUALO) model. The multi-objectives like wire length, area, and penalty function are taken into consideration.

Representation and assessment of spatial design using a hierarchical graph neural network: Classification of shopping center types

The assessment and prediction of spatial designs are essential in the building industry, where the primary challenge include finding a way to represent spatial designs and a numeric method to extract pattern. Herein, a shopping center type classification task was used to illustrate the application of the graph structure and hierarchical graph neural network (GNN) for the floor plan representation and classification. A graph dataset consisting of 359 s floor plans was established and used to train three different GNNs in two groups of experiments. The results showed that the test accuracies of the three GNNs were higher than those obtained with multinomial logistic regression and a support vector machine with Weisfeiler–Lehman kernel, and the differentiable pooling GNN with node function labels achieved the highest accuracy (70%). These findings indicate the advantages of GNNs, particularly the hierarchical pooling algorithm, and demonstrate their potential in spatial design embedding and assessment.

The role of latent representations for design space exploration of floorplans

Floorplans often require considering numerous factors, from the layout size to cost, numeric attributes such as room sizes, and other intrinsic properties such as connectivity between visible regions. Representing these complex factors is challenging, but doing so in a representative and efficient way can enable new modes of design exploration. Existing image and graph-based approaches of floorplans’ representation often failed to consider low-level space semantics, structural features, and space utilization with respect to its future inhabitants, which are all the critical elements to analyze design layouts. We present a latent-space representation of floorplans using gated recurrent unit variational autoencoder (GRU-VAE), where floorplans are represented as attributed graphs (encoded with the abovementioned features). Two local search approaches are presented to efficiently explore the latent space for optimizing and generating new floorplans for the given environment. Semantic, structural, and visibility metrics are evaluated individually and as a combined objective for optimizations.

The effects of floor plan representations on preferences for apartments

In the real-estate industry, floor plans are commonly used to communicate spatial layouts of housing alternatives to house hunters. Using the method of stated preferences, this research investigates whether lay-individuals’ preferences for layout attributes differ when floor plans versus text descriptions are used to measure preferences for build-to-rent apartments. The study involved 417 student respondents evaluating four hypothetical apartments twice, with the apartments varying in two focal attributes, layout orientation, and dining space status. Findings from the experiment indicate that floor plan representations of apartments are rated higher overall than text representations; however they also suggest that the effects of the two focal attributes on apartment preferences are larger for text than floor plan formats. Further, effects of the attributes on apartment preference ratings are shown to depend on the participants’ user goal and on their level of attribute knowledge. The main contribution of this research is that it demonstrates how representation format influences housing preferences, and further, how lay-individuals’ judgements of layout attributes depend on the individual’s goals and their knowledge of the attributes. These findings are relevant for future stated preference studies and for real estate agents and property developers when considering what information to provide to prospective buyers and renters of sight-unseen residential property.

Graph-based generative representation learning of semantically and behaviorally augmented floorplans

Floorplans are commonly used to represent the layout of buildings. Research works toward computational techniques that facilitate the design process, such as automated analysis and optimization, often using simple floorplan representations that ignore the space’s semantics and do not consider usage-related analytics. We present a floorplan embedding technique that uses an attributed graph to model the floorplans’ geometric information, design semantics, and behavioral features as the node and edge attributes. A long short-term memory (LSTM) variational autoencoder (VAE) architecture is proposed and trained to embed attributed graphs as vectors in a continuous space. A user study is conducted to evaluate the coupling of similar floorplans retrieved from the embedding space for a given input (e.g., design layout). The qualitative, quantitative, and user study evaluations show that our embedding framework produces meaningful and accurate vector representations for floorplans. Besides, our proposed model is generative. We studied and showcased its effectiveness for generating new floorplans. We also release the dataset that we have constructed. We include the design semantic attributes and simulation-generated human behavioral features for each floorplan in the dataset for further study in the community.

Design of indoor navigation system for buildings with complex hierarchical structure

There is currently a wide variety of navigation system, which allow determining the exact GPS coordinates and building a route taking based on the specified parameters. However, such systems are not suitable for indoor use, mostly due to no access to the floor plans. In view of this, it is relevant to minimize the time of searching for the location of a particular object, including in a building with complex hierarchical structure. The article examines the theoretical and practical developments in the sphere of navigation, conducts their comparative analysis, which indicated the need for designing the module for indoor navigation in a multi-storey building, considering the peculiarities of its floor plan. As a result, the authors designed the structure of the indoor navigation module in a building with complex hierarchical structure using the graph theory for detecting the shortest route and affine transformation algorithms for graphical representation of floor plan of a building on the example of the main building of the Nosov Magnitogorsk State Technical University. The article provides the description of its subsystems and blocks, as well as instruments for determining geopositioning of the object. The authors outline the prospects for the development of indoor navigation system, taking into account the peculiarities of creating electronic floor plans of a building based on the graph theory, as well as development of the algorithm for modification of the parameters of the existing 3D-objects. As a result of full implementation of the project, there will be designed the system of indoor navigation in a multi-storey building with complex hierarchical structure using a mobile app; it will help to easily find the geopositioning of the object and shortcuts.

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Three-dimensional integrated circuit (3D IC) technology offers a potential breakthrough to enable a paradigm-shift strategy, called “more than Moore,” with novel features and advantages over the conventional 2D process technology. By having three-dimensional interconnections, 3D IC provides substantial wirelength reduction and a massive amount of bandwidth, which gives significant performance improvement to overcome many of the nontrivial challenges in semiconductor industry. Moreover, 3D integration technology enables to stack disparate technologies with various functionalities into a single system-in-package (SiP), introducing “true 3D IC” design. As the first physical design (PD) step, IC floorplanning takes a crucial role to determine IC’s overall design qualities such as footprint area, timing closure, power distribution, thermal management, and so on. However, lack of efficient 3D floorplanning algorithms that practically implement advantages of 3D integration technology is a critical bottleneck for PD automation of 3D IC design and implementation. 3D floorplanning (or packing, block partitioning) is a well-known NP-hard problem, and most of 3D floorplanning algorithms rely on heuristics and iterative improvements. Thus, developing complete and efficient 3D floorplan representations is important, since floorplan representation provides the foundation of data structure to search the solution space for 3D IC floorplanning. A well-defined floorplan representation provides a well-organized and cost-effective methodology to design high-performance 3D IC. We propose a new 3D IC floorplan representation methodology using corner links and partial order . Given a fixed number of cuboidal blocks and their volume, algorithmic 3D floorplan representations describe topological structure and physical positions/orientations of each block relative to the origin in the 3D floorplan space. In this article, (1) we introduce our novel 3D floorplan representation, called corner links representation , (2) we analyze the equivalence relation between the corner links representation and its corresponding partial order representation , and (3) we discuss several key properties of the corner links representation and partial order representation. The corner links representation provides a complete and efficient structure to assemble the original 3D mosaic floorplan. Also, the corner links representation for the non-degenerate 3D mosaic floorplan can be equivalently expressed by the four trees representation . The partial order representation defines the topological structure of the 3D floorplan with three transitive closure graphs (TCG) for each direction and captures all stitching planes in the 3D floorplan in the order of their respective directions. We demonstrate that the corner links representation can be reduced to its corresponding partial order representation, indicating that the corner links representation shares well-defined and -studied features/properties of 3D TCG-based floorplan representation. If the partial order representation describes relations between any pairs of blocks in the 3D floorplan, then the floorplan is a valid floorplan. We show that the partial order representation can restore the absolute coordinates of all blocks in the 3D mosaic floorplan by using the given physical dimensions of blocks.

Performance evaluation of heuristic algorithms in floor planning for ASIC design

A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.

Stochastic-based placement template generator for analog IC layout-aware synthesis

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

3D VLSI Non-Slicing Floor Planning using Modified Corner List Representation

Background: Floor planning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floor plan, the total area occupied by the modules should be minimum. So, non-slicing floor plan is used to find an optimal floor plan layout. To represent non-slicing floor plan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floor planning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floor plan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.

Recent Developments in Floorplan Representations

Recent Developments in Floorplan Representations

Another Optimal Binary Representation of Mosaic Floorplans

Another Optimal Binary Representation of Mosaic Floorplans

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

Floorplan representation is a fundamental issue in designing a VLSI floorplanning algorithm as the representation has a great impact on the feasibility and complexity of floorplan designs. This survey paper gives an up-to-date account on various nonslicing floorplan representations in VLSI floorplanning.

A simple optimal binary representation of mosaic floorplans and Baxter permutations

Mosaic floorplans are rectangular structures subdivided into smaller rectangular sections and are widely used in VLSI circuit design. Baxter permutations are a set of permutations that have been shown to have a one-to-one correspondence to objects in the Baxter combinatorial family, which includes mosaic floorplans. An important problem in this area is to find short binary string representations of the set of n-block mosaic floorplans and Baxter permutations of length n. The best known representation is the Quarter-State Sequence which uses 4n bits. This paper introduces a simple binary representation of n-block mosaic floorplan using 3n−3 bits. It has been shown that any binary representation of n-block mosaic floorplans must use at least (3n−o(n)) bits. Therefore, the representation presented in this paper is optimal (up to an additive lower order term).

Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

Abstract —Placement is important in VLSI physical design as it determines the time-to-market and chip’s reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS’s search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS. Index Terms—Design, system, aided, floorplanning, VLSI, representation, circuits, algorithm, scale, optimization. I. I NTRODUCTION In the modern IC design flow, a placement of an IC is a schematic representation of placement of its major functional blocks. As the Very Large Scale Integration (VLSI) chip keeps shrinking in size, many factors such as the total area [1-2], wirelength [3-5], power consumption [6-7] and congestion reduction [8-9] will affect the reliability and efficiency of the chip. Hence, to cope up with these issues, efficient placement plays a very crucial role as far as the quality of the VLSI design is concerned. The VLSI placement design problem is well-known as the NP-hard problem and hence it is difficult to find exactly optimal solution in practical applications [10-11]. In order to solve this combinatorial optimization problem, placement layout is tackled mathematically in order to be optimized using the tools such as mathematical optimization or artificial intelligence (AI) technique. Many approaches [1], have been proposed in the literature with different modeling representations [12-15] and optimization methods [2], [5], [16-17] to enhance the quality of the placement design. To facilitate a good placement, it is necessary to develop an effective model for blocks placement to reduce the dead space area as well as minimizing the placement runtime. II. P

Multi-bend bus-driven floorplanning considering fixed-outline constraints

The rapid rate of technological advances makes it necessary for very large scale integration (VLSI) floorplanning to consider not only interconnect constraints, but also fixed-outline constraints. In this paper, we propose a new approach to address the problem of Bus-Driven Floorplanning (BDF) within a fixed die. By providing the width and height of a chip, a set of circuit blocks and the bus specifications (i.e., the width of each bus and the blocks that the bus needs to go through), the approach will generate a final floorplan that satisfies the following requirements: (a) all blocks are packed within the fixed outline, (b) all buses are routable and (c) the floorplan area and total bus area are minimized. Based on the deterministic algorithm Less Flexibility First (LFF), our approach does not need to resort to a floorplan representation and functions very well in fixed-outline floorplanning. Our approach places no limitations on the shape of the buses, and the processes of block packing and bus packing proceed simultaneously. According to the experimental results, our approach can generate a good solution with a lower percentage of dead space, a shorter total length of all buses and a shorter run time, even under fixed-outline constraints. In addition, our algorithm works well for large and complex test cases that have not been studied in previous research.

Analog Placement Based on Symmetry-Island Formulation

To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetric-feasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first linear-time-packing algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B*-tree representation, we propose automatically symmetric-feasible (ASF) B*-trees to directly model the placement of a symmetry island. We then present hierarchical B*-trees (HB*-trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetry-island formulation. In particular, the packing time for an ASF-B*-tree or an HB*-tree is the same as that for a plain B*-tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the best-published quality and runtime efficiency for analog placement.