Floating-point Unit Research Articles

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required processing effort, we systematically select instruction sequences that maximise error-rate. The application to a post-layout pipelined floating-point unit, which is implemented in 45 nm process technology, demonstrates the effectiveness and practicability of our PUF design. Finally, DTA-PUF requires up to 50× fewer instructions than existing software processor PUF designs, limiting processing costs and resulting in up to 26% power savings.

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Approximate computing has emerged as a promising design alternative for delivering power-efficient systems and circuits by exploiting the inherent error resiliency of numerous applications. The current article aims to tackle the increased hardware cost of floating-point multiplication units, which prohibits their usage in embedded computing. We introduce AFMU (Approximate Floating-point MUltiplier), an area/power-efficient family of multipliers, which apply two approximation techniques in the resource-hungry mantissa multiplication and can be seamlessly extended to support dynamic configuration of the approximation levels via gating signals. AFMU offers large accuracy configuration margins, provides negligible logic overhead for dynamic configuration, and detects unexpected results that may arise due to the approximations. Our evaluation shows that AFMU delivers energy gains in the range 3.6%–53.5% for half-precision and 37.2%–82.4% for single-precision, in exchange for mean relative error around 0.05%–3.33% and 0.01%–2.20%, respectively. In comparison with state-of-the-art multipliers, AFMU exhibits up to 4–6× smaller error on average while delivering more energy-efficient computing. The evaluation in image processing shows that AFMU provides sufficient quality of service, i.e., more than 50 db PSNR and near 1 SSIM values, and up to 57.4% power reduction. When used in floating-point CNNs, the accuracy loss is small (or zero), i.e., up to 5.4% for MNIST and CIFAR-10, in exchange for up to 63.8% power gain.

Parallel simulation method of GNSS multipath signal based on GPU

In order to solve the problems of the traditional GNSS multipath signal simulation methods, such as the complexity increases linearly with the number of multipath signals, inconvenient parameter updating and long operation time, a GPU based GNSS multipath signal parallel simulation method is proposed. Based on Farrow variable fractional delay filter, an independent parallel computing model of multi-channel filter coefficients is established, and a large number of floating-point units in GPU are used for parallel computing and filtering. Aiming at the performance bottleneck of this method, the optimization strategy of asynchronous parallel execution is given. The computer simulation results show that the complexity and operation time of the proposed method will not increase with the increase of the number of multipath signals. For the GNSS direct signal with sampling rate of 75MHz and time length of 1s, the maximum time consuming of the proposed method to generate 50 ∼ 1000 multipath signals is 158.6ms. Compared with the method of serial simulation on CPU, the proposed method speeds up to about 9.5 times, and the real-time simulation of multipath signals in complex environment can be realized.

FPGA accelerator for CNN: an exploration of the kernel structured sparsity and hybrid arithmetic computation

The deployment of large-scale deep neural networks on field programmable gate array (FPGA) platforms is severely hindered by the high requirements on computational resources and off-chip data bandwidth. Traditional nonstructured sparsity algorithms can efficiently reduce the nonzero weights of neural network models. However, the nonstructured sparse connections across channels also degrade the degree of computational parallelism and consequently seriously deteriorate the performance of the FPGA accelerator. We propose an FPGA accelerator by exploring the kernel structured sparsity and hybrid arithmetic computation for the convolutional neural network (CNN). On the one hand, we introduce a hardware-friendly kernel pruning method to reduce the number of arithmetic operations of the CNN model. Our proposed method maintains high accuracy (achieving a less than 0.32% accuracy loss) and achieves a high degree of parallelism. On the other hand, we design a specific hybrid arithmetic computation for the FPGA accelerator to speed up the performance of the pruned CNN model. The FPGA accelerator consists of only 64 sets of hybrid 8-bit and 16-bit floating-point units for the convolution operation. Experiments on VGGNet16 demonstrate that the proposed FPGA accelerator achieves a state-of-the-art 5 × convolution operation reduction and a 3 × parameter compression. The proposed FPGA accelerator is able to perform at 13.2 FPS, and the corresponding energy efficiency can be boosted up to 1.9 image / J.

Boundary Scan Architecture for a Double Precision Floating Point Subtractor

The boundary scan logic for testing was developed in order to make the process of testing easier for System-on-Chip (SoC) [1] architectures. The proposed work focuses on designing a boundary scan logic for a 64-bit floating-point subtractor unit. The TAP controller designed is capable of executing the three mandatory Joint Test Action Group (JTAG) instructions of the IEEE 1149 standard. The testing architecture has the potential to not only test the functionality of the core logic but also to test single stuck-at faults for all the inputs and outputs of the core logic. A provision for bypassing the core logic was made in order to skip the IC while testing numerous ICs together. A simulation was also performed to demonstrate the above procedures. The designed module can further be used in a larger circuit with other ICs [2]containing a similar boundary scan structure with individual TAP controllers.

Development of Library Components for Floating Point Processor

This paper deals with development of an n-bit binary to decimal conversion, decimal to n bit binary conversion and decimal to IEEE-754 conversion for floating point arithmetic logic unit (FPALU) using VHDL. Normally most of the industries now a days are using either 4-bit conversion of ALU or 8-bit conversions of ALU, so we have generalized this, thus we need not to worry about the bit size of conversion of ALU. It has solved all the problems of 4-bit, 8-bit, 16-bit conversions of ALU’s and so on. Hence, we have utilized VHSIC Hardware Description Language and Xilinx in accomplishing this task of development of conversions processes of ALU

Design and Implementation of a 32-bit Floating Point Unit

A Floating Point Unit is a math co-processor that is in the most demand of Digital Signal Processing (DSP), Processors and more. It is used to perform functions or operations on floating point numbers like addition, subtraction, multiplication, division, square root and more. It is specifically designed to carry out mathematical operations and it can be emulated in CPU. Floating point unit is a common operation used in advanced Digital Signal Processing and various processor applications. The aim was to develop an optimized floating point unit so that the delay was reduced and efficiency was increased. The floating point unit has been written according to IEEE 754 standard and the entire design has been coded in Verilog HDL. The results are improved by 12% with the usage of Vedic multiplier that is a delay of 4.450ns as compared to 5.123ns with an array multiplier. Designs can be further optimized using low power designing techniques at architectural level. Different behaviour can be observed for different size and technologies.

Arbitrary Reduced Precision for Fine-grained Accuracy and Energy Trade-offs

Full-precision Floating-Point Units (FPUs) can be a source of extensive hardware overhead (power consumption, area, memory footprint, etc.). As several modern applications feature an inherent tolerance to precision loss, a new computing paradigm has emerged: Transprecision Computing (TC). TC proposes several tools and techniques that trade precision for energy efficiency. However, most of these tools require developers to rewrite part or all of their existing software stacks, which is often infeasible, complex, or requires extensive development efforts. In addition to their intrusiveness, TC tools can only simulate the impact of precision loss, and they do not provide corresponding hardware designs that take advantage of the simulations.This work proposes a non-intrusive hardware-oriented approach, requiring no modification of source code that applies approximations at the low-level in assembly. The approach can be used to approximate virtually all types of executable binaries (bare-metal applications, single−/multi-threaded user applications, OS/RTOS, etc.). We introduce AxQEMU: a software based on the well known QEMU dynamic binary translator. We demonstrate how our approach can determine the effects of FP approximations on application-level Quality of Result (QoR), and how it interfaces with other tools from the literature. A hardware-level case study on a 28-nm FD-SOI implementation is presented, demonstrating how fine-grained energy/accuracy trade-offs can be made thanks to floating-point arbitrary reduced precision (ARP). For instance, considering the well-known arclength FP application, FPU computation energy savings of up to 19.4% were achieved with an accuracy threshold of 10 significant digits, and up to 60.7% with a 4-digit accuracy when using ARP. These savings compared favorably to the limited 7.7% saving afforded by using standard variable type optimization tools.

Design and analysis of high performance and low power FFT for DSP datapath using Vedic Multipliers

ABSTRACT Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.

FPGA‐based implementation of floating point processing element for the design of efficient FIR filters

Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross-Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.

Design And Optimization Of Floating Point Division And Square Root Using Minimal Device Latency

New microprocessors have become a compulsory feature of floating-point support. In recent years, multiple generations of floating-point units (FPU’s) have been seen by leading architectures. Although the introduction of addition and multiplication has been increasingly effective, the support of division as well as square root will have remained uneven. The types of algorithms employed, as well as the quality and efficiency of the implementations, are drastically different. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and a radix-16 floating-point squareroot. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and aradix-16 floating-point squareroot. Speculation between successive radix-4 incarnations is used to achieve a reduced timing. In digit-recurrence implementations, there are three separate components: initialization, digital repeats, and rounding. The repetition of the digit is the iterative component and for multiple loops it follows the same logic. The initialization and rounding steps are partly shared by the division and square root, although each has a separate logic for digital iterations. The result is a floating-point divider and square root with low latency, requiring double, single S and half-precision division of standardized operandsand 11, 6, and 4 result cycles, and 15, 8, and 5 cycles of square root cycles. One or two additional cycles are required in the case S of subnormal operand(s) or result

Intelligent Wireless Ultrasonic Device for Damage Detection of Metallic Structures

In today’s world, it is necessary to monitor structures for possible damages. A failure to monitor the structures properly can cause structural catastrophe. Many researchers have worked on the low-power ultrasonic device to monitor the structures. In this research, we present an intelligent ultrasonic device (IUD) to monitor and detect the damages on the structures. The device uses microcontroller, actuator interface circuit, sensor interface circuit and radio frequency (RF) modem. The microcontroller has in-built high-speed analog-to-digital converter (ADC), digital-to-analog converter (DAC) and floating-point unit for signal processing. The controller generates the tone-burst signal and sends it to actuator interface circuit. The actuator interface circuit conditions the received signal from the microcontroller and drives the Piezoelectric Transducer (PZT) actuator. The actuator generates an ultrasonic wave in the structure. The wave is then sensed by PZT sensors. The sensor interface circuit selects the signal from desired PZT sensor and sends it to the microcontroller for further processing. The microcontroller digitizes the signal and computes the damage index and only if the damage is severe, it will send data wirelessly to the nearby PC. To test the device, iron specimen was prepared, PZT actuator and PZT sensor was mounted on it. The artificial crack was then induced on the specimen. The ultrasonic wave was then collected from the structure. By analyzing the ultrasonic wave, the device successfully detected the induced crack in the structure. The future work will be to use GSM modem so that the device can be monitored in the real time from the remote location.

FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

The slowdown of Moore's law and the power wall necessitates a shift toward finely tunable precision (a.k.a. transprecision) computing to reduce energy footprint. Hence, we need circuits capable of performing floating-point operations on a wide range of precisions with high energy proportionality. We present FPnew, a highly configurable open-source transprecision floating-point unit (TP-FPU), capable of supporting a wide range of standard and custom FP formats. To demonstrate the flexibility and efficiency of FPnew in general-purpose processor architectures, we extend the RISC-V ISA with operations on half-precision, bfloat16, and an 8-bit FP format, as well as SIMD vectors and multiformat operations. Integrated into a 32-bit RISC-V core, our TP-FPU can speedup the execution of mixed-precision applications by 1.67× with respect to an FP32 baseline, while maintaining end-to-end precision and reducing system energy by 37%. We also integrate FPnew into a 64-bit RISC-V core, supporting five FP formats on scalars or 2, 4, or 8-way SIMD vectors. For this core, we measured the silicon manufactured in Globalfoundries 22FDX technology across a wide voltage range from 0.45 to 1.2 V. The unit achieves leading-edge measured energy efficiencies between 178 Gflop/sW (on FP64) and 2.95 Tflop/sW (on 8-bit mini-floats), and a performance between 3.2 and 25.3 Gflop/s.

A Customized Floating-point Processor Design for FPGA and ASIC based Thermal Compensation in High-precision Sensing

There are many types of sensors which require large dynamic range as well as high accuracy at the same time. Barometric altimeter is an example of such sensors. The signal processing techniques in the sensors are normally implemented using Field Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). The sensing variable in such type of the sensors is unwantedly environment dependent. So, for ensuring accuracy of the sensors this environmental dependency is minimized using the modeling and compensation techniques. In this work we have proposed a digital architecture for a programmable high precision computational unit which can be implemented in the FPGA or ASIC running the sensing algorithm of the sensors. This architecture can be used to implement polynomial compensation and it also supports reading and writing of the corresponding calibration coefficients even after the development of the sensors. Moreover, the architecture is platform independent. The architecture have been simulated for different FPGAs and ASIC and it has fulfilled the speed, accuracy and programmability requirements of the type of the sensors. The architecture has also been implemented and verified in a prototype of the barometric pressure sensor on Spartan-6 FPGA.

Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a general-purpose, ultraefficient chiplet-based architecture for data-parallel FP workloads. We have manufactured a prototype of the chiplet’s computational core in Globalfoundries 22FDX process and demonstrate more than 5x improvement in energy efficiency on FP intensive workloads compared to CPUs and GPUs. The compute capability at high energy and area efficiency is provided in “Snitch: A tiny pseudo dual-issue processor for area and energy efficient execution of floating-point intensive workloads,” IEEE Trans. Comput., containing eight small integer cores, each controlling a large floating-point unit (FPU). The core supports two custom ISA extensions: The SSRs extension elides explicit load and store instructions by encoding them as register reads and writes (“Stream semantic registers: A lightweight RISC-V ISA extension achieving full compute utilization in single-issue cores,” IEEE Trans. Comput.). The floating-point repetition extension decouples the integer core from the FPU allowing floating-point instructions to be issued independently. These two extensions allow the single-issue core to minimize its instruction fetch bandwidth and saturate the instruction bandwidth of the FPU, achieving FPU utilization above 90%, with more than 40% of core area dedicated to the FPU.

Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform

With the ever-growing trends in the latest technologies, digital signal processing is one of the known platforms which is used for many applications. RISC processor is the main element in all high-speed digital signal processing applications. The aim is to develop a RISC processor by including a single precision floating point unit in the instruction set along with other instructions and a complex multiplication instruction as it is commonly used in the DSP application. The floating-point unit is written according to the IEEE 754 standard and to introduce Vedic mathematics concept to compare and estimate the performance in terms of delay. The idea is to provide an optimized floating-point arithmetic unit and thereby provide an additional feature for the RISC processor instruction set. By using the Vedic multiplier, the delay is reduced by 55% compared to the normal array multiplier. The entire design is coded in Verilog HDL simulated on Xilinx ISE 14.7 platform.

Efficient Floating-Point Givens Rotation Unit

High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. FPGA implementation results are also presented and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

Acceleration Techniques using Reconfigurable Hardware for Implementation of Floating Point Multiplier

A multiplier plays a vital part in multimedia and digital signal processors. The integer unit alone cannot achieve the desired computational speed required by modern applications. Unit specially designed to carry out operations on floating point numbers is required also commonly known as floating-point unit. The IEEE 754 standard is used for defining the format of floating point number which is widely accepted. Basically, two formats are used for representing the floating point numbers, single precision which works on 32- bit floating point numbers whereas double precision working on 64 bit. Though the number of bits on which double precision operates doubles as compared to single precision number, it is hardly used due to its requirement of very large memory and also the delay generated for the IEEE-754 standard floating point multiplication. This is the mojor reason for its rare implementation in designs requiinge high computing speed.[1] In this paper we are proposing three efficient algorithms for enhancing the speed and optimizing the area required for implementing single precision floating point multiplication. Also compared the results in terms of power dissipation, execution time and area requirement for the implementation with the conventional methods used. Here the algorithms are implemented and analyzed by using the most popular semi-custom design tool Vivado ISE 2015 and is synthesized by using Artix-7 FPGA and the same is reflected in the mathematical model purposed for each circuit.

Error minimization based on multi-objective finite control set model predictive control for matrix converter in DFIG

Matrix Converter (MC) has many advantages such as capability of bi-directional energy conversion, no need for DC bus and high value filters. However, modulation methods are very difficult and require high computational effort. Therefore, Multi-objective Finite Control Set Model Predictive Control (MFCS-MPC) has been implemented to simplify the complexity of this topology. However, the weakness of this control method is using mathematical model and affected by parameter mismatches due to the external disturbances, frequency and temperature variations. In this study, past errors of rotor current are added to the cost function and the weighting factors are adjusted with the Fuzzy Decision Making (FDM) approach. Due to the combination of these two methods, a robust system is obtained that can operate even in model-plant mismatch. The proposed algorithm is implemented using the TMS320F28335 Digital Signal Processor (DSP), a 32-bit floating-point processor operating at 150 MHz. Results obtained from simulation and experimental setup are compared with the current literature studies and the performance of the proposed method is confirmed.