Floating-point Unit Research Articles

A Decomposition Workflow for Integrated Circuit Verification and Validation

This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.

A Numerical Relay Implementation for Overcurrent Protection Based on ARM Cortex – M4 Microprocessor

Numerical overcurrent protection relays are the most extensively used devices to safeguard the power system from detrimental faults which might lead to a catastrophe. This paper presents a practical implementation of a numerical overcurrent protection relay based on ARM Cortex – M4 microcontroller embedded with a floating-point unit which has ability to perform complex calculation operations with a great accuracy for real-time protection algorithms. In order to implement, the system is designed to capture analog values of input currents by using Hall current sensors, analog conditioning circuits and 12 – bit A/D converters. Based on the measured input current values, a real-time signal processing algorithm for overcurrent protection is applied to produce an inverse - time characteristic according to the IEEE Standard C37.112-1996. The experimental results demonstrate that our numerical relay produces great performances in the real-time and has ability to protect electrical components from exceeded current faults satisfying the IEEE standard for overcurrent relays.

Implementation of Control Algorithms in Small Embedded Systems

This work describes how a control algorithm can be implemented in a small (8-bit) microcontroller for the main purpose of merging embedded systems and control theory in electrical engineering undergraduate classes. Two different methods for discretizing the control expression are compared: Euler transformation and bilinear transformation. The sampling rate’s impact on the algorithm is discussed and theoretical results are verified by an application to a temperature control system in a heating plant. Four control algorithms are compared: PID and PI algorithms discretized with Euler and bilinear transformation, respectively. It is shown that for the heating plant used in this work, a bilinear PI algorithm implemented in a small 8-bit microcontroller outperforms a commercial controller from Panasonic. It is also demonstrated that all the derived algorithms can be implemented using integer calculations only, obviating the need for expensive and time-consuming floating-point calculations. This work bridges the gap between control theory equations and the implementation of control systems in small embedded systems with no inherent floating-point processing power.

A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors

The slowdown in technology scaling puts architectural features at the forefront of the innovation in modern processors. This article presents a Metric-Guided Method (MGM) that extends Top-Down analysis with carefully selected, dynamically adapted metrics in a structured approach. Using MGM, we conduct two evaluations at the microarchitecture and the Instruction Set Architecture (ISA) levels. Our results show that simple optimizations, such as improved representation of CISC instructions, broadly improve performance, while changes in the Floating-Point execution units had mixed impact. Overall, we report 10 architectural insights—at the microarchitecture, ISA, and compiler fronts—while quantifying their impact on the SPEC CPU benchmarks.

Pre-calculated duty cycle optimization method based on genetic algorithm implemented in DSP for a non-inverting buck-boost converter

This study presents a pre-calculated duty cycle optimization method based on the genetic algorithm for a non-inverting buck-boost converter (NIBBC). In this method, the duty cycles are calculated via a discrete model estimation of NIBBC. Despite its high computational time requirements, this method can find solutions to problems that other methods cannot overcome due to their lack of linearity, continuity, or other features. This algorithm is developed using the TMS320F28335 digital signal processor, which is a 32-bit floating point processor operating at 150 MHz. The robustness and stability of this method at varying input voltages, loads, and parameters are then analyzed following the IEEE and IEC standards. The experimental results verify the simulation results and highlight the efficiency, power quality, wide output voltage range, and stability of the proposed method.

Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI

In this article, we present Ara, a 64-bit vector processor based on the version 0.5 draft of RISC-V's vector extension, implemented in GlobalFoundries 22FDX fully depleted silicon-on-insulator (FD-SOI) technology. Ara's microarchitecture is scalable, as it is composed of a set of identical lanes, each containing part of the processor's vector register file and functional units. It achieves up to 97% floating-point unit (FPU) utilization when running a 256 × 256 double-precision matrix multiplication on 16 lanes. Ara runs at more than 1 GHz in the typical corner (TT/0.80 V/25 °C), achieving a performance up to 33 DP-GFLOPS. In terms of energy efficiency, Ara achieves up to 41 DP-GFLOPS W <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> under the same conditions, which is slightly superior to similar vector processors found in the literature. An analysis on several vectorizable linear algebra computation kernels for a range of different matrix and vector sizes gives insight into performance limitations and bottlenecks for vector processors and outlines directions to maintain high energy efficiency even for small matrix sizes where the vector architecture achieves suboptimal utilization of the available FPUs.

Generation scheme of chirp scaling phase functions based on floating‐point CORDIC processor

This study presents a chirp scaling (CS) phase function generation scheme based on CORDIC algorithm, it adopts single precision floating-point CORDIC processor to implement a variety of non-linear operations which are involved in CS synthetic aperture radar (SAR) imaging algorithm. We extend the range of convergence of CORDIC algorithm and reduce the data width in rotation unit module by adopting a hardware resource reduction scheme. We also adopt a unified CORDIC processor to achieve square root, multiplication, and division operation, which can substitute multiple single-function processors and simplify the complicate arithmetic in CS algorithm. As a proof of concept, we verify the performance of the proposed design scheme on Xilinx XC7VX690T FPGA platform, it is also applied to 16384 × 16384 points target SAR imaging system, the FPGA resource occupancy of the CS phase function generation module demonstrates that the usage of CORDIC processor can effectively save the consumption of hardware resources, and the maximum operating frequency is acceptable. The accuracy of phase functions can satisfy the engineering requirements.

Toward energy efficient microcontrollers and Internet-of-Things systems

In this paper, energy consumption of five common microcontroller (MCU) boards running a set of common functions and operations is studied. This includes a study of changing clock-speed, serial bit-rate, analog-to-digital conversion sampling rate, and compiler optimizations effects on the energy consumption. Additionally, the effect of using the on-chip floating point units (FPU) on the energy consumption is investigated. Results obtained in this study show that subtraction consumes slightly more energy than addition on all boards. Division consumes significantly more energy than any other operation. MCUs equipped with an FPU unit consume significantly less energy when performing an operation using the appropriate hardware unit. 8-bit, 16-bit, or 32-bit operations on a 32-bit MCU consume about the same amount of energy. The detailed results reported in this work serve as a valuable guideline for designers and developers to help build more energy-efficient embedded systems.

An optimal device sizing for a performance-driven and area-efficient subthreshold cell library for IoT applications

Ultra-low power design techniques specifically subthreshold designs, play a vital role in Internet of things systems that survive on limited power budget or harvested energy sources. In this paper, the width and length of a transistor operating at subthreshold region are optimized considering the nano-scale effects such as reverse short channel effect and inverse narrow width effect, which improves performance, reduces area, minimizes sensitivity to process variation and reduces energy consumption. A subthreshold standard cell library consisting of 45 standard cells is designed. The physical synthesis of ISCAS′85 benchmark circuits and a floating point unit shows that energy savings in area-mapped design are up to 23% whereas area savings in performance-mapped design are up to 30%. The measurement results from a test chip fabricated in industrial 130 nm technology demonstrate a performance improvement of up to 27%, reduction in delay variability of up to 24% and energy savings of 18%.

A Highly Efficient Heterogeneous Processor for SAR Imaging.

The expansion and improvement of synthetic aperture radar (SAR) technology have greatly enhanced its practicality. SAR imaging requires real-time processing with limited power consumption for large input images. Designing a specific heterogeneous array processor is an effective approach to meet the power consumption constraints and real-time processing requirements of an application system. In this paper, taking a commonly used algorithm for SAR imaging—the chirp scaling algorithm (CSA)—as an example, the characteristics of each calculation stage in the SAR imaging process is analyzed, and the data flow model of SAR imaging is extracted. A heterogeneous array architecture for SAR imaging that effectively supports Fast Fourier Transformation/Inverse Fast Fourier Transform (FFT/IFFT) and phase compensation operations is proposed. First, a heterogeneous array architecture consisting of fixed-point PE units and floating-point FPE units, which are respectively proposed for the FFT/IFFT and phase compensation operations, increasing energy efficiency by 50% compared with the architecture using floating-point units. Second, data cross-placement and simultaneous access strategies are proposed to support the intra-block parallel processing of SAR block imaging, achieving up to 115.2 GOPS throughput. Third, a resource management strategy for heterogeneous computing arrays is designed, which supports the pipeline processing of FFT/IFFT and phase compensation operation, improving PE utilization by a factor of 1.82 and increasing energy efficiency by a factor of 1.5. Implemented in 65-nm technology, the experimental results show that the processor can achieve energy efficiency of up to 254 GOPS/W. The imaging fidelity and accuracy of the proposed processor were verified by evaluating the image quality of the actual scene.

Design of a High Speed and Area Efficient Novel Adder for AES Applications

In the design of VLSI circuits, there is huge power consumption because of circuit complexity. It is known that the demand for portable equipment is rapidly increasing now a days. Recently power efficient circuit designs have been concentrated. In complex arithmetic circuits adder is the most important building block. These are widely used in some other applications also like Central Processing Units, Arithmetic Logic Units and floating-point units. In case of cache memory access and in digital signal processing, these are used for address generation. Adders are most significant in control systems also. The speed of a processor and system accuracy is based on the performance of this adder. Regularly, Ripple Carry Adder is elected for two N-bit numbers adder due to fast design time of these RCAs among various other types of adders. Even though if RCA has fast design time, but it is limited in time because of that each full adder must wait for the carry bits of previous full adder blocks. A carry tree adder is proposed in this paper which is efficiently implemented technique at gate level for decreasing the delay and decreasing the memory usage.

Development of a RISC-V-Conform Fused Multiply-Add Floating-Point Unit

Despite the fact that the open-source community around the RISC-V instruction set architecture is growing rapidly, there is still no high-speed open-source hardware implementation of the IEEE 754-2008 floating-point standard available. We designed a Fused Multiply-Add Floating-Point Unit compatible with the RISC-V ISA in SystemVerilog, which enables us to conduct detailed optimizations where necessary. The design has been verified with the industry standard simulation-based Universal Verification Methodology using the Specman e Hardware Verification Language. The most challenging part of the verification is the reference model, for which we integrated the Floating-Point Unit of an existing Intel processor using the Function Level Interface provided by Specman e. With the use of Intel's Floating-Point Unit we have a ``known good" and fast reference model. The Back-End flow was done with Global Foundries' 22 nm Fully-Depleted Silicon-On-Insulator (GF22FDX) process using Cadence tools. We reached 1.8 GHz over PVT corners with a 0.8 V forward body bias, but there is still a large potential for further RTL optimization. A power analysis was conducted with stimuli generated by the verification environment and resulted in 212 mW.

Design of area-efficient IIR filter using FPPE

Floating point arithmetic circuits provide wide dynamic range and high precision, and they are widely used in scientific computing and signal processing applications, but the complexity increases in hardware implementations of floating point units. In VLSI design architecture, many applications suffer in size of the components used in logical operations. The aim of reducing architecture is to gain reduction in power loss and also in area, but the reduction in size of the components leads to an increase in delay and memory. Hence, to overcome these limitations and to optimize the area, a novel design of floating point processing element (FPPE) architecture is proposed in this work with a smaller number of logical components and registers. A partially folded arithmetic function architecture is modeled for the design of an infinite impulse response (IIR) filter using FPPE and implemented on a field programmable gate array (FPGA) with efficient area. FPGAs are widely used in the implementation of floating point computing modules due to the increase in gate density and embedded arithmetic cores. Synthesis results prove that the proposed design of the IIR filter provides efficient area compared with existing works. The modules are designed in Verilog and implemented on Xilinx FPGAs.

A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2k-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm2. The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.

Significance-Driven Data Truncation for Preventing Timing Failures

The continuous scaling of transistor sizes and the increased parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, typically designers adopt pessimistic timing margins, which are estimated under rare worst-case conditions. In this paper, we present a technique that mitigates such pessimistic margins by minimizing the number of timing failures. In particular, we propose a method that minimizes the number of long latency paths within each processor pipeline stage and constrains them in as few stages as possible. Such a method allows us not only to reduce the timing failures but also to limit the potential error-prone locations to only a few pipeline stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and truncate the bitwidth of the operands in the few remaining long latency paths by setting a number of less significant bits (LSBs) to a constant value of zero. Such a truncation may incur quality loss, but this is limited since it is applied only to the LSBs of the few operands that may activate the confined error-prone long latency paths. To evaluate the efficiency of our method, we perform post-place and route dynamic timing analysis based on real operands extracted from a variety of applications. This helps to estimate the bit-error rate, while considering the data-dependent path excitation. When applied to an IEEE-754 compatible double precision floating point unit (FPU), the proposed approach reduces the timing failures by $216.25 {\times }$ on average compared to the reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45-nm process. Our results show that the path shaping alone introduces a negligible 0.25% area and 5.7% power overheads with no performance cost. Finally, we demonstrate that by combining the path shaping with aggressive operand bitwidth truncation, we enable power savings up to 44.7% due to the substantially reduced switching activity at minimal quality loss.

FPGA Realization of Hyperbolic Function

Machine Learning (ML) is applied in many real world applications. Artificial Neuron (AN) is the main building block of Artificial Neural Networks (ANN) which is the backbone of ML. ML algorithms for different applications like image and speech recognition etc., speech with large data are implemented on workstations with GPUs. However, the power of ML techniques for real time applications like monitoring, control and diagnostics, typical in power and process plant is still in nascent stage. Most of these applications require FPGA realization of ANNs. Realization of AN with both sigmoid and hyperbolic tangent activation functions along with results is reported in this paper. Design of building blocks consisting of Floating Point Unit (FPU) and Function approximation (FA) are presented. Implementation using Verilog HDL along with results of accuracy with simulated inputs and gate count and timing diagrams are presented.

A Flexible 12-Lead/Holter Device with Compression Capabilities for Low-Bandwidth Mobile-ECG Telemedicine Applications.

In recent years, a number of proposals for electrocardiogram (ECG) monitoring based on mobile systems have been delivered. We propose here an STM32F-microcontroller-based ECG mobile system providing both long-term (several weeks) Holter monitoring and 12-lead ECG recording, according to the clinical standard requirements for these kinds of recordings, which in addition can yield further digital compression at stages close to the acquisition. The system can be especially useful in rural areas of developing countries, where the lack of specialized medical personnel justifies the introduction of telecardiology services, and the limitations of coverage and bandwidth of cellular networks require the use of efficient signal compression systems. The prototype was implemented using a small architecture, with a 16-bits-per-sample resolution. We also used a low-noise instrumentation amplifier TI ADS1198, which has a multiplexer and an analog-to-digital converter (16 bits and 8 channels) connected to the STM32F processor, the architecture of which incorporates a digital signal processing unit and a floating-point unit. On the one hand, the system portability allows the user to take the prototype in her/his pocket and to perform an ECG examination, either in 12-lead controlled conditions or in Holter monitoring, according to the required clinical scenario. An app in the smartphone is responsible for giving the users a friendly interface to set up the system. On the other hand, electronic health recording of the patients are registered in a web application, which in turn allows them to connect to the Internet from their cellphones, and the ECG signals are then sent though a web server for subsequent and ubiquitous analysis by doctors at any convenient terminal device. In order to determine the quality of the received signals, system testing was performed in the three following scenarios: (1) The prototype was connected to the patient and the signals were subsequently stored; (2) the prototype was connected to the patient and the data were subsequently transferred to the cellphone; (3) the prototype was connected to the patient, and the data were transferred to the cellphone and to the web via the Internet. An additional benchmarking test with expert clinicians showed the clinical quality provided by the system. The proposed ECG system is the first step and paves the way toward mobile cardiac monitors in terms of compatibility with the electrocardiographic practice, including the long-term monitoring, the usability with 12 leads, and the possibility of incorporating signal compression at the early stages of the ECG acquisition.

Enhancing Accuracy and Dynamic Range of Scientific Data Analytics by Implementing Posit Arithmetic on FPGA

The high performance, power efficiency and reconfigurable characteristic of FPGA attract more and more attention in big data processing. In scientific data analytics, besides the consideration of computing performance, accuracy of the results and dynamic range of data representation are critical features that must be considered. At present, the floating-point IP cores in FPGA design use IEEE standard for floating-point arithmetic – IEEE 754. For FPGA based scientific data application, improving existing floating-point IP cores is a significant way to obtain better results. Posit is a floating-point arithmetic format first proposed by John L. Gustafson in 2017. In posit, the variable precision and efficient representation of exponent contribute a higher accuracy and larger dynamic range than IEEE 754. This work researches on the FPGA implementation of posit arithmetic for extending floating-point IP cores for FPGA based scientific data analytics. We design the logic for hardware implementation and implement it on FPGA. We compare the precision representation, dynamic range and performance of implemented posit FPU (Floating-Point Unit) with IEEE 754 floating-point IP cores. Posit exhibits better superiority in precision representation and dynamic range than IEEE 754, and through further optimization of the implementation, posit can be a good candidate for floating-point IP cores.

An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies

With the modern semiconductor supply chain, the ownership of both intellectual property (IP) and integrated circuit (IC) cannot be guaranteed. The IP piracy may take place at the untrusted IC designer or untrusted foundry without the knowledge of the original IP owner. The untrusted foundry can also perform IC piracy with reverse engineering of GDSII, overproducing the number of ICs, and shipping out-of-spec/defective devices. A holistic solution is proposed to protect the ownership of both IP owners and IC designers. In this solution, a dynamically obfuscated wrapper for split test (DOST) and a secure split test methodology together aim at preventing IP overusing at multiple abstraction levels and enabling IC designers to fully control the production, test, and authentication processes. DOST has been implemented and validated on video graphics array-liquid crystal display, floating-point and graphics unit, Leon3, and Leon3mp benchmarks. DOST enables the structural tests in the locked mode and the functional tests in the functionally unlocked mode. The results show that the proposed method is highly robust against IP and IC piracies with an insignificant area (1.381%) and power (1.276%) overhead.

Approximate Computing Using Multiple-Access Single-Charge Associative Memory

Memory-based computing using associative memory is a promising way to reduce the energy consumption of important classes of streaming applications by avoiding redundant computations. A set of frequent patterns that represent basic functions are pre-stored in Ternary Content Addressable Memory (TCAM) and reused. The primary limitation to using associative memory in modern parallel processors is the large search energy required by TCAMs. In TCAMs, all rows that match, except hit rows, precharge and discharge for every search operation, resulting in high energy consumption. In this paper, we propose a new Multiple-Access Single-Charge (MASC) TCAM architecture which is capable of searching TCAM contents multiple times with only a single precharge cycle. In contrast to previous designs, the MASC TCAM keeps the match-line voltage of all miss-rows high and uses their charge for the next search operation, while only the hit rows discharge. We use periodic refresh to control the accuracy of the search. We also implement a new type of approximate associative memory by setting longer refresh times for MASC TCAMs, which yields search results within 1–2 bit Hamming distances of the exact value. To further decrease the energy consumption of MASC TCAM and reduce the area, we implement MASC with crossbar TCAMs. Our evaluation on AMD Southern Island GPU shows that using MASC (crossbar MASC) associative memory can improve the average floating point units energy efficiency by 33.4, 38.1, and 36.7 percent (37.7, 42.6, and 43.1 percent) for exact matching, selective 1-HD and 2-HD approximations respectively, providing an acceptable quality of service (PSNR > 30 dB and average relative error <10 percent). This shows that MASC (crossbar MASC) can achieve 1.77X (1.93X) higher energy savings as compared to the state of the art implementation of GPGPU that uses voltage overscaling on TCAM.