Design And Optimization Of Floating Point Division And Square Root Using Minimal Device Latency

Abstract

New microprocessors have become a compulsory feature of floating-point support. In recent years, multiple generations of floating-point units (FPU’s) have been seen by leading architectures. Although the introduction of addition and multiplication has been increasingly effective, the support of division as well as square root will have remained uneven. The types of algorithms employed, as well as the quality and efficiency of the implementations, are drastically different. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and a radix-16 floating-point squareroot. Here a floating-point division and square root unit is provided that implements a radix-64 floating-point division and aradix-16 floating-point squareroot. Speculation between successive radix-4 incarnations is used to achieve a reduced timing. In digit-recurrence implementations, there are three separate components: initialization, digital repeats, and rounding. The repetition of the digit is the iterative component and for multiple loops it follows the same logic. The initialization and rounding steps are partly shared by the division and square root, although each has a separate logic for digital iterations. The result is a floating-point divider and square root with low latency, requiring double, single S and half-precision division of standardized operandsand 11, 6, and 4 result cycles, and 15, 8, and 5 cycles of square root cycles. One or two additional cycles are required in the case S of subnormal operand(s) or result