Abstract

We have been developing the floating-point unit (FPU) based on single-flux-quantum (SFQ) logic toward a highspeed and low-power superconducting graphical processing unit. The floating-point divider is the most complicated circuit element of the SFQ FPU. We designed the SFQ floating-point divider on the basis of Goldschmidt's algorithm, which is one of multiplicative hardware algorithms for division. Because the multiplies in the divider can be used for multiplication in the FPU by employing the multiplicative division algorithm, the FPU can be efficiently designed by using the designed floating-point divider. We show the circuit scale estimation of the FPU that uses the designed divider as a function on floating-point precision. We measured the 4-bit and 11-bit SFQ floating-point dividers implemented by the AIST 10 kA/cm2 Nb advanced process. The 11-bit SFQ floating- point divider is composed of 8091 Josephson junctions and can be applied to half-precision FPU. We confirmed correct operation of the 4-bit SFQ divider by low-frequency function test.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.