Floating-point Multiplication Research Articles

SIMPLE EFFECTIVE FAST INVERSE SQUARE ROOT ALGORITHM WITH TWO MAGIC CONSTANTS

The purpose of this paper is to introduce a modification of Fast Inverse Square Root (FISR) approximation algorithm with reduced relative errors. The original algorithm uses a magic constant trick with input floating-point number to obtain a clever initial approximation and then utilizes the classical iterative Newton-Raphson formula. It was first used in the computer game Quake III Arena, causing widespread discussion among scientists and programmers, and now it can be frequently found in many scientific applications, although it has some drawbacks. The proposed algorithm has such parameters of the modified inverse square root algorithm that minimize the relative error and includes two magic constants in order to avoid one floating-point multiplication. In addition, we use the fused multiply-add function and iterative methods of higher order in the second iteration to improve the accuracy. Such algorithms do not require storage of large tables for initial approximation and can be effectively used on field-programmable gate arrays (FPGAs) and other platforms without hardware support for this function.

Merged Floating Point Multipliers

Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.

Merged Floating Point Multipliers

Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.

Implementation of Parallel and Pipeline Scheme in the Standard Floating Point Adder to Improve the Speed

In real time Signal Processing applications, the analogue signal is over sampled as per the Nyquist criterion in order to avoid the aliasing effect. Floating Point (FP) adder is used in the floating point Multiplier Accumulator Content (MAC) for real time Digital Signal Processing(DSP) applications. The heart of any real time DSP processor is floating point MAC. Floating Point MAC is constructed by Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters. FIR filters are stable than IIR filters because the impulse response is finite in FIR. Hence, for stable applications FIR filters are preferred. These FIR filters are intern constituted by FP adder, FP multiplier and shifter. In conventional floating point adder the two floating point numbers are added in series. Series means one after the other so the computation speed is less. In series fashion adding the floating point numbers means definitely it furnishes more delay[1] because in the addition of floating point numbers, along with the addition of mantissas; computation is required for both signs and exponents also. Hence, the processing speed is slow for computing the floating point numbers compared with fixed point numbers. Therefore, in order to increase the speed of operation for floating point addition in real time application i.e., to add 16- samples at a time which are in floating notation; a parallel and pipe line technique is going to be incorporated to the two bit floating point architecture. Before developing such novel architecture, a novel algorithm is developed and after, the novel architecture is developed. The total work is simulated by Modelsim 10.3c tool and synthesized by Xilinx 13.6 tool.

Comparative Review of Floating-Point Multiplier Systems

Comparative Review of Floating-Point Multiplier Systems

A Modified Double-Precision Floating-Point Multiplier To Achieve Reduced Hardware Utilization

The DP(Double-Precision) floating-point multiplier require a bulky 52x52 mantissa multiplications. The enactment of the DP floating number multiplication predominantlybe influenced by on the area and speed. This paper presents a improveduniquemethod to diminution this huge multiplicationpracticeof mantissa. The UTmethodpermitsusinga reducedquantityof multiplication hardware equaled to the conventional method. In old-fashionedschemeaccumulation of the partial products are independentlycompleted and it may perhapsyieldextraperiod of time in contrast to thesuggested method. In the suggestedprocess the partial products are parallel added with the multiplication actions and it canreduce the time delay. The method wasinstigated using VerilogHDL with Xilinx 14.2 ISE tools on Virtex-5 FPGA.

Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

Low power single precision BCD floating–point Vedic multiplier

In this paper, the Binary coded decimal floating-point multiplier (BCD-FPM) and Binary floating-point multiplier (BFPM) with binary to BCD (B2BCD) converter are proposed using Urdhva-Tiryakbhyam (UT) sutra. Two methods are proposed for BCD-FPM and comparison is made between BCD-FPM and BFPM with B2BCD converter. The designs are modelled in Verilog HDL and synthesized based on the 90nm standard cell library in Cadence EDA Tool. Comparisons are based on the synthesis report generated by Cadence RTL complier and implemented in Encounter RTL TO GDSII system. The results show that BCD-FPM has better performance in terms of delay and power. The power for Method II gets reduced by 59.47% and 73.40% when compared with Method I and BFPM with B2BCD converter respectively. The delay for Method II gets reduced by 6.9% than Method I and 30.37% than BFPM with B2BCD converter. The pipelined architecture is designed for Method II as it is efficient than other multipliers, whose delay is reduced by 65.82% after pipelining.

Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

Efficient half-precision floating point multiplier targeting color space conversion

Color Space Conversion (CSC) in image processing applications, demands computationally simple floating point multipliers consuming less area and power. This necessitates the design and realization of the same meeting the aforesaid concerns. This paper makes one such contribution in the form of a New Bit Pair Recoding (NBPR) algorithm for realizing a Data Length Reduction (DLR)-based 16-bit Half-Precision Floating Point Multiplier (HPFPM). This algorithm with merged partial product addition achieves partial product height reduction from n to $\frac {n}{4}$ for an n × n multiplier by evading 2’s complement, negative encoding and sign extension. HPFPM is implemented on both Application Specific Integration Circuit (ASIC) with TSMC 180, 130 and 65 nm technologies and Xilinx-Virtex-5 and Virtex-7 Field Programmable Gate Array (FPGA) families. HPFPM synthesized on TSMC 65nm consumes 51% and 55.8% of area and power respectively, with 0.6835% error when compared with full width half-precision multiplier. Also, HPFPM for RGB-YUV-RGB and RGB-YCbCr-RGB conversion reduces the area, power consumption by 11%, 12% respectively, with 93.2% improved accuracy, when compared with truncated 32-bit single-precision floating point multipliers (SPFPMs). The converted image is evaluated using Peak-Signal-to-Noise-Ratio (PSNR) and Mean Square Error (MSE) in Matlab for quantifying HPFPM suitability for CSC in imaging.

Implementation of multi-precision floating point divider for high speed signal processing applications

The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Particularly Newton–Raphson (NR) based division algorithm is popular choice to SRT division algorithms. This paper proposes 32-bit FP division using NR computational division technique with pipelining method capable of doing high speed signal processing operations. The proposed divider used as IP core and make it as optimal choice to speed up FP operations. It improves rounding accuracy in addition with reduction in area overhead. The NR computational calculations are implemented by iteratively using 32-bit FP multiplier and adder. The key module used for calculating significand (mantissa) part is 24-bit Wallace tree multiplier using carry save adders. The Wallace multiplier provides higher computational speed, hence, is effectively utilized as a part of FP divider. The proposed pipelined FP divider is fully combinational circuit with clock and data gating applied to reduce the dynamic power consumption, delay and area overhead designed for signal processing applications. It also improves the accuracy of the result. The operands are represented and operated using IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array.

Performance Analysis of Floating Point Multiplier Designs

Performance Analysis of Floating Point Multiplier Designs

Hardware-Software Co-design to Accelerate Neural Network Applications

Many applications, such as machine learning and data sensing, are statistical in nature and can tolerate some level of inaccuracy in their computation. A variety of designs have been put forward exploiting the statistical nature of machine learning through approximate computing. With approximate multipliers being the main focus due to their high usage in machine-learning designs. In this article, we propose a novel approximate floating point multiplier, called CMUL, which significantly reduces energy and improves performance of multiplication while allowing for a controllable amount of error. Our design approximately models multiplication by replacing the most costly step of the operation with a lower energy alternative. To tune the level of approximation, CMUL dynamically identifies the inputs that produces the largest approximation error and processes them in precise mode. To use CMUL for deep neural network (DNN) acceleration, we propose a framework that modifies the trained DNN model to make it suitable for approximate hardware. Our framework adjusts the DNN weights to a set of “ potential weights ” that are suitable for approximate hardware. Then, it compensates the possible quality loss by iteratively retraining the network. Our evaluation with four DNN applications shows that, CMUL can achieve 60.3% energy efficiency improvement and 3.2× energy-delay product (EDP) improvement as compared to the baseline GPU, while ensuring less than 0.2% quality loss. These results are 38.7% and 2.0× higher than energy efficiency and EDP improvement of the CMUL without using the proposed framework.

Efficient FPGA Implementations of Pair and Triplet-Based STDP for Neuromorphic Architectures

Synaptic plasticity is envisioned to bring about learning and memory in the brain. Various plasticity rules have been proposed, among which spike-timing-dependent plasticity (STDP) has gained the highest interest across various neural disciplines, including neuromorphic engineering. Here, we propose highly efficient digital implementations of pair-based STDP (PSTDP) and triplet-based STDP (TSTDP) on field programmable gate arrays that do not require dedicated floating-point multipliers and hence need minimal hardware resources. The implementations are verified by using them to replicate a set of complex experimental data, including those from pair, triplet, quadruplet, frequency-dependent pairing, as well as Bienenstock–Cooper–Munro experiments. We demonstrate that the proposed TSTDP design has a higher operating frequency that leads to $2.46\times $ faster weight adaptation (learning) and achieves 11.55 folds improvement in resource usage, compared to a recent implementation of a calcium-based plasticity rule capable of exhibiting similar learning performance. In addition, we show that the proposed PSTDP and TSTDP designs, respectively, consume $2.38\times $ and $1.78\times $ less resources than the most efficient PSTDP implementation in the literature. As a direct result of the efficiency and powerful synaptic capabilities of the proposed learning modules, they could be integrated into large-scale digital neuromorphic architectures to enable high-performance STDP learning.

A high-speed fixed width floating-point multiplier using residue logarithmic number system algorithm

The Residue Logarithmic Number System (RLNS) in digital mathematics allows multiplication and division to be performed considerably quickly and more precisely than the extensively used Floating-Point number setups. RLNS in the pitch of large scale integrated circuits, digital signal processing, multimedia, scientific computing and artificial neural network applications have Fixed Width property which has equal number of in and out bit width; hence, these applications need a Fixed Width multiplier. In this paper, a Fixed Width-Floating-Point multiplier based on RLNS was proposed to increase the processing speed. The truncation errors were reduced by using Taylor series. RLNS is the combination of both the residue number system and the logarithmic number system, and uses a table lookup including all bits for expansion. The proposed scheme is effective with regard to speed, area and power utilization in contrast to the design of conservative Floating-Point mathematics designs. Synthesis results were obtained using a Xilinx 14.7 ISE simulator. The area is 16,668 µm2, power is 37 mW, delay is 6.160 ns and truncation error can be lessened by 89% as compared with the direct-truncated multiplier. The proposed Fixed Width RLNS multiplier performs with lesser compensation error and with minimal hardware complexity, particularly as multiplier input bits increment.

An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients

Integer discrete cosine transform (DCT) reduces the complexity of the transform kernel in High Efficiency Video Coding (HEVC) by eliminating the need for floating point multiplications. However, the dynamic range of integer DCT is large and therefore hardware cost is high. In this brief, a new transform kernel for HEVC is proposed which uses a new set of real-valued DCT coefficients. The proposed real-valued DCT reduces the hardware cost and the processing time by reducing the complexity as well as intermediate data length. However, it maintains coding performance similar to that of the integer DCT. Further, a hardware efficient data flow model of 2D-DCT architecture is also presented, which shows that a transpose memory of 15-bit data depth is enough to process 9-bit residual data. Field-programmable gate array implementation of the proposed 1-D DCT architecture reduces the area-delay product and power by 37.5% and 43.4%, respectively, as compared to that of the integer DCT. The proposed architecture requires 88.6K logic gates to produce a constant throughput of 32 samples per clock and it operates at 256.4 MHz on CMOS 90-nm ASIC platform.

Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication

Approximate multipliers enable the saving of area and power for implementation of many modern error-resilient compute-intensive applications. In this paper, we first propose a novel error-configurable minimally biased approximate integer multiplier (MBM) design. The proposed MBM design is devised by coupling a unique error-reduction mechanism with an approximate log based integer multiplier. Next, we propose an optimization (by removing leading-one detection and barrel shifting logic) of the MBM and a class of state-of-the-art approximate integer multipliers (DRUM and SSM), so that they can be efficiently used in approximate floating-point (FP) multipliers. Then, we propose a set of new approximate FP multipliers and we show that these FP multipliers lie on the Pareto front on the design spaces of area versus error and power versus error. We synthesize the designs using the TSMC 45-nm standard-cell library. Results show that the MBM integer design offers optimal points in the design space, offering up to 75% area reduction and 84% power reduction with $57 \times $ power and $28 \times $ area improvement for less than 25% peak error, 7% mean error, and 4% error bias, when compared with the IEEE-754 single-precision FP multiplier. We also perform application-level evaluations of the proposed approximate integer and FP multipliers, showing that our proposed multipliers enable significant power and area reduction with minimal degradation in applications’ output quality.

Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit

Cellular neural networks (CeNNs) have been widely adopted in image processing tasks. Recently, various hardware implementations of CeNNs have emerged in the literature, with Field Programmable Gate Array (FPGA) being one of the most popular choices due to its high flexibility and low time-to-market. However, CeNNs typically involve extensive computations in a recursive manner. As an example, to simply process an image of 1,920 × 1,080 pixels requires 4--8 Giga floating point multiplications (for 3 × 3 templates and 50–100 iterations), which needs to be done in a timely manner for real-time applications. To address this issue, in this article, we propose a compressed CeNN framework for efficient FPGA implementations. It involves various techniques, such as incremental quantization and early exit, which significantly reduces computation demands while maintaining an acceptable performance. Particularly, incremental quantization quantizes the numbers in CeNN templates to powers of two, so that complex and expensive multiplications can be converted to simple and cheap shift operations, which only require a minimum number of registers and logical elements (LEs). While a similar concept has been explored in hardware implementations of Convolutional Neural Networks (CNNs), CeNNs have completely different computation patterns, which require different quantization and implementation strategies. Experimental results on FPGAs show that incremental quantization and early exit can achieve a speedup of up to 7.8× and 8.3×, respectively, compared with the state-of-the-art implementations, while with almost no performance loss with four widely adopted applications. We also discover that different from CNNs, the optimal quantization strategies of CeNNs depend heavily on the applications. We hope that our work can serve as a pioneer in the hardware optimization of CeNNs.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.