Floating-point Multiplication Research Articles

Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

The small floating-point (SFP) multiplier proposed by Xilinx is utilized to implement the convolution neural networks (CNNs). This scheme can balance the resource usage of look-up tables (LUTs) and digital signal processing blocks (DSPs) so that high compute density is achieved on Field Programmable Gate Arrays (FPGAs). In addition, this scheme can quantize the CNNs with several simple scaling operations rather than a lengthy compute intensive retraining process. However, the mantissa field of SFP multiplier is required to be less than or equal to 3-bit, thus significantly restricts the application of this scheme. To figure out this issue, we implement the SFP multiplier in the logarithmic domain such that the multiplication is performed by the addition with the aid of logarithmic and anti-logarithmic converters that is referred to as small logarithmic floating-point (SLFP) multiplier. Compared to SFP multiplier (3-bit mantissa), the proposed SLFP multiplier can support multiple accuracy levels ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) with a relatively low overhead ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\mathbf {\mathrm {\sim }} 3\mathbf {\times }$ </tex-math></inline-formula> LUT6s). Moreover, we utilize the look-ahead carry chain to reduce the delay of addition so that the proposed SLFP multiplier can operate at 650MHz. As a result, the latency (1.5ns, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mathbf {\times }$ </tex-math></inline-formula> clock cycle) and throughput (650MOPS) of proposed SLFP multiplier ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) are the same as the SFP multiplier (3-bit mantissa). In the end, the implementation of MobileNet proves that the accuracy level of SFP multiplier (3-bit mantissa) is not sufficient, which can be solved by the proposed SLFP multipliers (5-bit mantissa).

Dendrocentric learning for synthetic intelligence.

Artificial intelligence now advances by performing twice as many floating-point multiplications every two months, but the semiconductor industry tiles twice as many multipliers on a chip every two years. Moreover, the returns from tiling these multipliers ever more densely now diminish because signals must travel relatively farther and farther. Although travel can be shortened by stacking tiled multipliers in a three-dimensional chip, such a solution acutely reduces the available surface area for dissipating heat. Here I propose to transcend this three-dimensional thermal constraint by moving away from learning with synapses to learning with dendrites. Synaptic inputs are not weighted precisely but rather ordered meticulously along a short stretch of dendrite, termed dendrocentric learning. With the help of a computational model of a dendrite and a conceptual model of a ferroelectric device that emulates it, I illustrate how dendrocentric learning artificial intelligence-or synthetic intelligence for short-could run not with megawatts in the cloud but rather with watts on a smartphone.

PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier With Unbiasedness and Configurability

Approximate computing is a promising alternative to improve energy efficiency for IoT devices on the edge. This work proposes a piecewise-linearly-approximated and unbiased floating-point approximate multiplier with run-time configurability. We provide a theoretically sound formulation that turns multiplication approximation to an optimization problem. With the formulation and findings, a multi-level architecture is proposed to easily incorporate run-time configurability and module execution parallelism. Finally, the proposed multiplier is further optimized to reduce the circuit implementation complexity, making the multiplier linearly dependent on the precision requirement, instead of quadratically or exponentially as in prior work. When compared to the prior state-of-the-art approximate floating-point multiplier, ApproxLP M. Imani <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al</i> , “ApproxLP: Approximate multiplication with linearization and iterative error control,” in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Proc. ACM/IEEE Des. Autom. Conf.</i> , 2019, pp. 1–6., the proposed multiplier outperforms in all the aspects including accuracy, area, and delay. By replacing a full-precision floating-point multiplier in GPU, the proposed design can improve the energy efficiency for various edge computing tasks. Even with Level 1 approximation, the proposed multiplier improves energy efficiency up to 20× for machine learning on CIFAR-10, with almost negligible accuracy loss.

Approximate Floating-Point Multiplier based on Static Segmentation

In this paper a novel low-power approximate floating-point multiplier is presented. Since the mantissa computation is responsible for the largest part of the power consumption, we apply a novel approximation technique to mantissa multiplication, based on static segmentation. In our approach, the inputs of the mantissa multiplier are properly segmented so that a small inner multiplier can be used to calculate the output, with beneficial impact on power and area. To further improve performance, we introduce a novel segmentation-and-truncation approach which allows us to eliminate the shifter normally present at the output of the segmented multiplier. In addition, a simple compensation term for reducing approximation error is employed. The accuracy of the circuit can be tailored at the design time, by acting on a single parameter. The proposed approximate floating-point multiplier is compared with the state-of-the-art, showing good performance in terms of both precision and hardware saving. For single-precision floating-point format, the obtained NMED is in the range 10−5–7 × 10−7, while MRED is in the range 3 × 10−3–1.7 × 10−4. Synthesis results in 28 nm CMOS show area and power saving of up to 82% and 85%, respectively, compared to the exact floating-point multiplier. Image processing applications confirm the expectations, with results very close to the exact case.

Logarithm-approximate floating-point multiplier

Approximate computing is a useful approach to save power and increase performance by trading Energy and accuracy. This paper proposes an efficient inexact floating-point (FP) multiplier using the idea of a semi-logarithm multiplier. In the proposed approximate FP multiplier, instead of the traditional mantissa multiplier, an approximate adder is used. The results show that the power consumption and delay of the proposed approximate FP multiplier have been decreased by 97% and 53% compared with the IEEE-754 single-precision exact FP multiplier. In addition, the proposed approximate FP multiplier provides an improvement of 81% in terms of area. Compared to the logarithm-approximate FP multiplier, the proposed inexact FP multiplier has 81%, 34%, and 34% savings in power, area, and delay parameters, respectively. High dynamic range (HDR) images are processed using the proposed approximate FP multiplier in smoothing and sharpening applications to show the quality of the proposed FP multiplier in image processing.

Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation

In this brief, a variable-precision approximate floating-point multiplier is proposed for energy efficient deep learning computation. The proposed architecture supports approximate multiplication with BFloat16 format. As the input and output activations of deep learning models usually follow normal distribution, inspired by the posit format, for numbers with different values, different precisions can be applied to represent them. In the proposed architecture, posit encoding is used to change the level of approximation, and the precision of the computation is controlled by the value of product exponent. For large exponent, smaller precision multiplication is applied to mantissa and for small exponent, higher precision computation is applied. Truncation is used as approximate method in the proposed design while the number of bit positions to be truncated is controlled by the values of the product exponent. The proposed design can achieve 19% area reduction and 42% power reduction compared to the normal BFloat16 multiplier. When applying the proposed multiplier in deep learning computation, almost the same accuracy as that of normal BFloat16 multiplier can be achieved.

Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT

Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(6, 9)$</tex-math></inline-formula> input and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(7, 8)$</tex-math></inline-formula> output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(6, 9)$</tex-math></inline-formula> input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Q(1, 14)$</tex-math></inline-formula> format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.

Fast Cardinality of Square Method

Multiplication is major concern in calculations. Performing multiplication on floating-point data is a long course of action and requires huge quantity of processing tremendous amount of handling time. By improve the fast speed of multiplication task overall speed of the system can be enhanced. The Bottleneck in the floating-point multiplication process is the multiplication of mantissas which need 53×53 bit integer multiplier for double precision floating-point numbers and Medic, and Chronic Signed digit algorithms exists to compare parameters like speed, complexity o f routing, pipe lining, resource required on FPGA. The comparison showed that Chronic Signed Digit Algorithm and Booth Multiplication Algorithm is better than Medic algorithm concerning speed and resources required on spartan3 FPGA

A 15-Gbps BiCMOS XNOR gate for fast recognition of COVID-19 in binarized neural networks

The COVID-19 pandemic is spreading around the world causing more than 177 million cases and over 3.8 million deaths according to the European Centre for Disease Prevention and Control. The virus has devastating effects on economies, health, and well-being of worldwide population. Due to the high increase in daily cases, the available number of COVID-19 test kits in under-developed countries is scarce. Hence, it is vital to implement an effective screening method of patients using chest radiography since the equipment already exists. With the presence of automatic detection systems, any abnormalities in chest radiography that characterizes COVID-19 can be identified. Several artificial-intelligence algorithms have been proposed to detect the virus. However, neural networks training is considered to be time-consuming. Since computations in training neural networks are spent on floating-point multiplications, high computational power is required. Multipliers consume the most space and power among all arithmetic operators in deep neural networks. This paper proposes a 15 Gbps high-speed bipolar-complementary-metal-oxide-semiconductor (BiCMOS) exclusive-nor (XNOR) gate to replace multipliers in binarized neural networks. The proposed gate can be implemented on BiCMOS-based field-programmable gate arrays (FPGAs). This will significantly improve the response time in identifying chest abnormalities in CT scans and X-rays.

Design and Implementation of Floating-Point Addition and Floating-Point Multiplication

Abstract: In this paper, we present the design and implementation of Floating point addition and Floating point Multiplication. There are many multipliers in existence in which Floating point Multiplication and Floating point addition offers a high precision and more accuracy for the data representation of the image. This project is designed and simulated on Xilinx ISE 14.7 version software using verilog. Simulation results show area reduction and delay reduction as compared to the conventional method. Keywords: FIR Filter, Floating point Addition, Floating point Multiplication, Carry Look Ahead Adder

Logic Design and Power Optimization of Floating-Point Multipliers.

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

Analysis of 16x16 Vedic and 16 Bit Floating Point Multiplier -A Comparative Study

Analysis of 16x16 Vedic and 16 Bit Floating Point Multiplier -A Comparative Study

Runtime accuracy alterable approximate floatingpoint multipliers

Modern systems demand high computational power within limited resources. Approximate computing is a promising approach to design arithmetic units with tight resources for error-tolerant applications such as image and signal processing and computer vision. A floating-point multiplier is one of the arithmetic units with the highest complexity in such applications. Designing a floating-point multiplier based on the approximate computing technique can reduce its complexity as well as increase performance and energy efficiency. However, an unknown error rate for upcoming input data is problematic to design appropriate approximate multipliers. The existing solution is to utilize an error estimator relying on statistical analysis. In this paper, we propose new approximate floating-point multipliers based on an accumulator and reconfigurable adders with an error estimator. Unlike previous designs, our proposed designs are able to change the levels of accuracy at runtime. Thus, we can make errors distributed more evenly. In contrast to other designs, our proposed design can maximize the performance gain since reconfigurable multipliers are able to operate two multiplications in parallel once the low accuracy mode is selected. Furthermore, we apply a simple rounding technique to approximate floating-point multipliers for additional improvement. Our simulation results reveal that our new method can reduce area by 70.98% when error tolerance margin of our target application is 5%, and when its error tolerance margin is 3%, our rounding enhanced simple adders-based approximate multiplier can save area by 65.9%, and our reconfigurable adder-based approximate multiplier with rounding can save the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.

SEOFP-NET: Compression and Acceleration of Deep Neural Networks for Speech Enhancement Using Sign-Exponent-Only Floating-Points

Numerous compression and acceleration strategies have achieved outstanding results on classification tasks in various fields. Nevertheless, the same strategies may yield unsatisfactory performance on regression tasks because the nature between regression and classification tasks differs. In this paper, a novel sign-exponent-only floating-point network (SEOFP-NET) technique is proposed to compress the model size and accelerate the inference time for speech enhancement, a regression task of speech signal processing. The proposed method compressed the sizes of deep neural network (DNN)-based speech enhancement models by quantizing the fraction bits of single-precision floating-point parameters during training. Before inference implementation, all parameters in the trained SEOFP-NET model are adjusted to accelerate the inference time by replacing the floating-point multiplier with an integer-adder. The experimental results indicate that the size of SEOFP-NET models can be significantly compressed by up to 81.249% without noticeably downgrading their speech enhancement performance, and the inference time can be accelerated to 1.212x compared with the baseline models. The results also verify that SEOFP-NET can cooperate with other efficiency strategies to achieve a synergy effect for model compression. In addition, results of a just noticeable difference experiment show that the listeners cannot facilely differentiate between the enhanced speech signals processed by the baseline model and SEOFP-NET. To the best of our knowledge, this study is one of the first works that aims to compress the model size and reduce the inference time of speech enhancement while maintaining satisfactory performance. The promising results confirm the potential applicability of SEOFP-NET to lightweight embedded devices.

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads

The frequent data movement between the processor and the memory has become a severe performance bottleneck for deep neural network (DNN) training workloads in data centers. To solve this off-chip memory access challenge, the 3-D stacking processing-in-memory (3D-PIM) architecture provides a viable solution. However, existing 3D-PIM designs for DNN training suffer from the limited memory bandwidth in the base logic die. To overcome this obstacle, integrating the DNN related logic near each memory bank becomes a promising yet challenging solution, since naively implementing the floating-point (FP) unit and the cache in the memory die incurs a large area overhead. To address these problems, we propose DLUX, a high performance and energy-efficient 3D-PIM accelerator for DNN training using the near-bank architecture. From the hardware perspective, to support the FP multiplier with low area overhead, an in-DRAM lookup table (LUT) mechanism is invented. Then, we propose to use a small scratchpad buffer together with a lightweight transformation engine to exploit the locality and enable flexible data layout without the expensive cache. From the software aspect, we split the mapping/scheduling tasks during DNN training into intralayer and interlayer phases. During the intralayer phase, to maximize data reuse in the LUT buffer and the scratchpad buffer, achieve high concurrency, and reduce data movement among banks, a 3D-PIM customized loop tiling technique is adopted. During the interlayer phase, efficient techniques are invented to ensure the input-output data layout consistency and realize the forward-backward layout transposition. Experiment results show that DLUX can reduce FP32 multiplier area overhead by 60% against the direct implementation. Compared with a Tesla V100 GPU, end-to-end evaluations show that DLUX can provide on average 6.3× speedup and 42× energy efficiency improvement.

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Approximate computing has emerged as a promising design alternative for delivering power-efficient systems and circuits by exploiting the inherent error resiliency of numerous applications. The current article aims to tackle the increased hardware cost of floating-point multiplication units, which prohibits their usage in embedded computing. We introduce AFMU (Approximate Floating-point MUltiplier), an area/power-efficient family of multipliers, which apply two approximation techniques in the resource-hungry mantissa multiplication and can be seamlessly extended to support dynamic configuration of the approximation levels via gating signals. AFMU offers large accuracy configuration margins, provides negligible logic overhead for dynamic configuration, and detects unexpected results that may arise due to the approximations. Our evaluation shows that AFMU delivers energy gains in the range 3.6%–53.5% for half-precision and 37.2%–82.4% for single-precision, in exchange for mean relative error around 0.05%–3.33% and 0.01%–2.20%, respectively. In comparison with state-of-the-art multipliers, AFMU exhibits up to 4–6× smaller error on average while delivering more energy-efficient computing. The evaluation in image processing shows that AFMU provides sufficient quality of service, i.e., more than 50 db PSNR and near 1 SSIM values, and up to 57.4% power reduction. When used in floating-point CNNs, the accuracy loss is small (or zero), i.e., up to 5.4% for MNIST and CIFAR-10, in exchange for up to 63.8% power gain.

A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

VLSI Design and Comparative Analysis of Several Types of Fixed and Simple Precision Floating Point Multipliers

Multiplication is an arithmetic operation that has a meaningful impact on the performance of several real-life applications, such as digital signal and image processing. Analysis and comparison of different types of fixed-point multipliers such as Wallace tree, array, and Booth-2 with truncated and non-truncated versions were included in this design. Fixed-point multipliers were used to design floating-point multipliers through a hardware description language. As a result, area and speed values were analyzed. Booth-2 fixed multiplier with truncation and RCA adders present both the longest delay and the largest area consumption. Wallace tree floating-point multiplier required the smallest area and the shortest delay. The 8-bit versions of fixed-point multipliers were physically synthesized, using the Alliance tools, to obtain the layout of the circuits. The integrated circuits were successfully fabricated in a 0.5-μm CMOS technology.

Design of FFT processor using low power Vedic multiplier for wireless communication

Digital Signal Processing (DSP) is a very significant and active research area. High throughput is a requirement for most wireless communication systems. The critical bottleneck that affects communication ability is the Fast Fourier Transform (FFT), which is the essence of most modulators. Currently, Floating point FFT processors have been used in Radar signal processing, fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real-time FFT processing. The multiplication limits the performance in terms of throughput of FFT. Consequently, there is a need for high speed and low power multiplier architectures with minor truncation error. The present paper presents a modified binary floating-point multiplier using Vedic mathematics and a modification in the previously published Vedic multiplier circuit has been proposed. The entire design has been implemented in Verilog HDL. Synthesis and simulations are done using Xilinx ISE Design Suite 14.5.The performance evaluation in terms of speed and area occupied is compared with the previously reported Vedic multiplier architectures. Using 90 nm technologies, the Power Delay Product (PDF) of the proposed Vedic multiplier gets reduced through KSA by 86.41% compared to the multipliers. The Vedic adder power is reduced by 45.9% when it is compared with the carry look-ahead adder. The overall power delay product is reduced around 55–60% through the FFT processor by using Vedic mathematics.

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.