An Optimized Architecture of HEVC Core Transform Using Real-Valued DCT Coefficients

Abstract

Integer discrete cosine transform (DCT) reduces the complexity of the transform kernel in High Efficiency Video Coding (HEVC) by eliminating the need for floating point multiplications. However, the dynamic range of integer DCT is large and therefore hardware cost is high. In this brief, a new transform kernel for HEVC is proposed which uses a new set of real-valued DCT coefficients. The proposed real-valued DCT reduces the hardware cost and the processing time by reducing the complexity as well as intermediate data length. However, it maintains coding performance similar to that of the integer DCT. Further, a hardware efficient data flow model of 2D-DCT architecture is also presented, which shows that a transpose memory of 15-bit data depth is enough to process 9-bit residual data. Field-programmable gate array implementation of the proposed 1-D DCT architecture reduces the area-delay product and power by 37.5% and 43.4%, respectively, as compared to that of the integer DCT. The proposed architecture requires 88.6K logic gates to produce a constant throughput of 32 samples per clock and it operates at 256.4 MHz on CMOS 90-nm ASIC platform.