Floating-gate Technique Research Articles

Low voltage EX-CCCII based on quasi-floating gate technique and its application as precision rectifier

This paper introduces a novel low-voltage low-power Extra-X Current Controlled Current Conveyor (EX-CCCII) based on quasi floating gate (QFG) MOSFET. The QFG technique is employed in low voltage applications and overcomes the limitation of the floating gate technique. The presented circuit is implemented at a supply voltage of ±0.5 V with a power consumption of 90 µW at 20 µA bias current. As an application, the proposed QFG based EX-CCCII is employed to realize a novel current mode precision rectifier circuit. This circuit can simultaneously provide positive and negative type half wave and full wave rectifiers with the same circuit configuration. Furthermore, the rectifier circuit has low input and high output impedance terminals making it suitable for cascading with other current mode circuits. All the results provided to verify the circuit performance are simulated using CADENCE VIRTUOSO SPECTRE simulator with 0.18 µm UMC CMOS technology process parameters. The simulation results confirm the theoretical concept.

A low-voltage highly linear OTA using bulk-driven floating gate MOSFETs

In this paper, a floating gate OTA using Flipped Voltage Follower (FG-FVF OTA) and its modified version with bulk-driven floating gate MOSFETs (BDFG-FVF OTA) are proposed. The FVF configuration is used to reduce the power consumption while the combination of bulk-driven and floating gate techniques is employed to enhance the linearity of the OTA. The proposed OTAs are compared with a floating gate OTA (FG OTA) to show the performance improvement. All the OTAs are designed and simulated in Candace Virtuoso tool using 0.18 μm CMOS process technology. The circuits are biased with ±0.5 V power supply. The simulation results show that the proposed BDFG-FVF OTA has less variation in transconductance for large range of input differential voltage as compared to FG OTA. BDFG-FVF OTA shows 8 dB improvement in HD3 for 0.2 Vpp differential voltage at 1 MHz frequency as compared to conventional FG OTA and its power consumption is 158 μW which is 36% lesser than that of FG OTA. All these improvements in proposed OTA are achieved at cost of 0.07% reduction in bandwidth. An application of proposed OTA is also presented in the form of universal Gm-C filter to ensure the workability of the proposed OTA.

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of $$-\,2$$ . Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/− 1 LSB and the INL is + 1.8/− 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is $$1.6\,\upmu$$ A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of $$400 \times 500\,{\mathrm{mm}}^2$$ .

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

A power-efficient reconfigurable amplifier with crossed cascode self-biasing

ABSTRACTA low power reconfigurable sensing amplifier for biomedical applications is proposed. Two cascode voltages in a telescopic amplifier are provided by using only one floating gate and a symmetrically cross self-biasing scheme. Complementary differential pairs and floating-gate techniques are employed to attain low electronic noise and bandwidth reconfigurability with low power consumption. To improve linearity in low frequency operation, gate-balanced pseudo resistors are adopted as feedback resistors. The power efficiency is optimised using a 1.8 V supply voltage with 30 nA current consumption in a 100 Hz bandwidth setting. The measured noise efficiency factor (NEF) is 1.88 with integrated input-referred noise. The dynamic range is above 61.7 dB.

Toward an innovative stochastic modeling of electric charges loss through dielectric

This paper deals with new stochastic modeling of very low tunneling currents in Non-Volatile Memories. For this purpose, we first develop current measurement method based on Floating Gate technique. In order to reach the long time behavior of electrical dynamic, we aim at using very basic tools (power supply, multimeter...) but still having a very good current resolution. Also, our measurement is led in a very particular low-noise environment (underground laboratory) allowing to keep the electrical contacts on the device under test as long as possible. After showing the feasibility of such measurements, we present a modeling approach of the charge loss process inside the Non-volatile Memories by using mathematical tool involving long memory effect. The model is based on stochastic counting process with memory effect yielding to a fractional relaxation equation for the charge loss over time. The main interest of the present model lies in the fact that the corresponding inversion problem involves only two parameters that can be carried out efficiently.

16-Channel Low Power CMOS Integrated Circuit for Detection of Auditory Nerve Signals

For sensorineural hearing loss, auditory perception can be activated by electrical stimulation of a nervous system via electrode implanted into cochlea or auditory nerves. As the tonotopic map of the human auditory nerve has not been absolutely identified, the recording of its signal with electrode is desirable to determine the map. This paper proposes a 16-channel analog front-end for auditory nerve signal detection. Its channel consists of an AC coupling circuit, a 4th-order Gm-C lowpass filter (LPF), and a single-slope analog-todigital converter (ADC). While blocking DC level, the AC coupling circuit transfers only AC signal. The Gm-C LPF is designed with operational transconductance amplifiers (OTAs) using floating-gate technique for small Gm. The channel-wise single-slope ADC is used because it has the small area and low power consumption. Experiment results show the prototype chip fabricated in 0.35-μm CMOS process has the bandwidth of 0.1 ~ 6.95 kHz with the gain of 19.9 dB, the effective resolution of 7.7 bits and the power consumption per a channel of 12 μW.

A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.

Floating-gate CMOS ternary latch

The design of a novel floating-gate CMOS ternary latch is presented. The design is based on a CMOS latch with level shifters that are realised using floating-gate techniques. The three stable operating points possessed by this circuit allow the cell to realise a ternary latch. The number of operating points possessed by the latch can be set using an external DC voltage. Measurement results from a fabricated prototype in a 0.5 µm CMOS technology are included to demonstrate the design presented.

Real-Time Reconfigurable Subthreshold CMOS Perceptron

In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

Spatial and energetical profiles of defects extracted from ultra-low level trap-assisted leakage current in non-volatile floating thin tunnel oxide memory devices by using direct and floating gate technique measurements

Stress induced leakage currents (SILC) remain one of the main reliability problems preventing further SiO 2 tunnel oxide thickness reduction in floating thin oxide (FLOTOX) memory devices. In this work, we present ultra-low level SILC current–voltage ( I– V) measurements performed by using the floating gate technique on 7–8 nm thick SiO 2 tunnel oxides and low-level measurements performed by direct technique measurements. Experimental characteristics obtained by the indirect measurement technique reached current levels as low as 2 × 10 −17 A. They exhibit new phenomena such as negative differential resistance behavior and current threshold voltages. A physical one-step tunneling model (A-mode), taking into account the influence of defects located in the bulk SiO 2, is proposed. Both spatial and energetical defect profiles are extracted from experimental data. We show that the new phenomena experimentally observed can be interpreted as a one step trap-assisted tunneling mechanism via defects located near the middle oxide, even for highly stressed components.

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.

A new structure to monitor electrical transients during programming of EEPROM memory cells

In this paper, we present an original test structure, representative of a FLOTOX (FLOating gate Thin OXide) EEPROM technology, that allows to monitor both the programming current (by direct measurement) and the floating gate potential (indirectly by the so-called floating gate technique) during write and erase operations. Experimental electrical transients are compared to simulations based on a simplified electrical model. It is then shown that these procedures can be powerfully applied to the study of endurance of EEPROM devices and of the evolution of their programming window with operating temperature.

New oxide quality characterization for charge leakage applications using the floating-gate technique

We report on the validation of a new characterization method dedicated to the tunnel oxide of electrically erasable programmable read-only memories. The present approach combines a dedicated test structure with sequential floating-gate measurements, allowing the screening of defective oxides in terms of charge leakage. We show that this floating-gate technique returns reliable information about retention capability of the thin tunnel oxide (7.5 nm) using a fast and non-destructive statistical test. Finally, quantitative information about tunnel oxide quality obtained with this new technique matches data obtained with charge-to-breakdown measurements.

A frequency delta-sigma analog-to-digital converter operating at a power-supply voltage of 0.6 V

This paper describes a delta-sigma analog-to-digital converter operating at a power supply voltage of 0.6 V. The converter is implemented in a standard AMS 0.6 µm double poly process, and consists of a frequency-delta-sigma modulator where the transistor threshold voltage is decreased by floating-gate techniques.

A general bulk-limited transport analysis of a 10 nm-thick oxide stress-induced leakage current

This paper describes the characteristics of steady-state stress-induced leakage current (SILC) of a 10-nm-thick oxide. Data are obtained by using the high resolution floating-gate technique, at room temperature as well as at higher temperatures (20–190°C). The results are interpreted by means of a new complete bulk-limited conduction theory, which generalizes the well-known Poole–Frenkel and Poole effects. This analysis leads us to argue that a thermally activated bulk-limited trap-assisted process dominates the steady-state SILC conduction mechanism in thick oxides at room/high temperature. Furthermore, it is shown that in thinner oxides, SILC conduction mechanism at room/high temperature can also be explained by the same bulk-limited theory.

Study of stress induced leakage current by using high resolution measurements

Abstract A thorough characterization of stress-induced leakage currents (SILCs) for a IOnm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.

Investigation of low field and high temperature SiO 2 and ONO leakage currents using the floating gate technique

In this work a critical analysis of the floating gate technique, for measurement of leakage currents <fA, is presented. Results obtained with thermal SiO 2 and with SiO 2/Si 3N 4/SiO 2 (ONO) triple stacked layer structures, at temperatures as high as 400°C, are shown. It is demonstrated that the floating gate technique offers an improved sensitivity and a better accuracy. Nevertheless, the existence of a trade off in terms of measurement time and equipment accuracy is noted. Concerning experimental results, a model based on a complete Fowler–Nordheim expression, completed with an ohmic leakage at electric fields ≈3 MV/cm, is found to fit SiO 2 data and to explain, at least qualitatively, ONO results.

Location and quantification of the interface defects in stressed LDD NMOSFETs using a combination of floating-gate and transconductance techniques, and charge-pumping methods

In sub-micrometre LDD NMOSFETs we were able to correlate an evolution of hot-carrier-induced gate currents obtained from floating-gate measurements with corresponding evolution of saturation transconductances. With this correlation, additional substrate current measurements, and the help of a 2D device simulation framework, we find that negative oxide-trapped charges of magnitude 2.5 × 1018 cm−3 are responsible for the experimental observations. This damage is located in the oxide at the edge of the gate over 100 Å (1 Å = 10−10 m) above the oxide–silicon interface, which is deep into the LDD structure and difficult to probe with the existing methods. Then we demonstrate how the in-channel interface states density can be profiled using a lateral-profiling charge-pumping technique. The coupling of the techniques mentioned above leads to the characterization of the entire oxide–silicon interface along the length of the gate. This is essential for the proper understanding of the directions for process improvements and the mechanisms of defect generation.

Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs

Propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs is modeled using measurements and 2-D device simulation. It is argued that the saturation of degradation is caused by the saturating nature of this degradation length, as opposed to decreasing lateral electric field maxima (E/sub m/) or increasing barrier height (/spl phi//sub it/) to defect creation. Two stage hot-carrier degradation was observed in our LDD NMOSFETs. The early mode (1000-3000 s) of the degradation is characterized by a sharp rate of degradation of the linear transconductance (g/sub m/), and a reduction in the substrate current (I/sub B/). In order to locate and quantify defects produced in this early mode degradation phase, we use the results of a combination of the floating gate technique and simultaneous measurements of the reverse (source and drain interchanged) saturation g/sub m/'s. These results help us build a 2-D simulation framework involving trapped negative charges in the oxide in the drain-side gate-edge region, partly under the gate and partly in the spacer region. We then use 2-D simulation and other measurements such as linear and saturation current degradation, I/sub B/ degradation, and charge pumping to confirm the location of the defects and help estimate their quantity. Simulation results also help us build an analytical model for defect propagation from the early mode to the late mode. The analytical model is seen to explain many features of the saturating nature of hot-carrier degradation.