Toward an innovative stochastic modeling of electric charges loss through dielectric

G Micolau,P Chiquet,C Abbas,C Ginoux,D Boyer,M Joelson,J Postel-Pellerin

doi:10.1051/e3sconf/20161204004

Abstract

This paper deals with new stochastic modeling of very low tunneling currents in Non-Volatile Memories. For this purpose, we first develop current measurement method based on Floating Gate technique. In order to reach the long time behavior of electrical dynamic, we aim at using very basic tools (power supply, multimeter...) but still having a very good current resolution. Also, our measurement is led in a very particular low-noise environment (underground laboratory) allowing to keep the electrical contacts on the device under test as long as possible. After showing the feasibility of such measurements, we present a modeling approach of the charge loss process inside the Non-volatile Memories by using mathematical tool involving long memory effect. The model is based on stochastic counting process with memory effect yielding to a fractional relaxation equation for the charge loss over time. The main interest of the present model lies in the fact that the corresponding inversion problem involves only two parameters that can be carried out efficiently.

Highlights

Flash memory cells are based on the floating gate technology principle [1]
Floating gate technologies consist in adding a second gate between the gate and the channel of a classical MOS transistor
As said in introduction, owing to the fact that these electrical models cannot be reached at very low current values, a valuable task for the future is to link our stochastic modeling that is available from datasets, with these electrical models (F-N and Poole Frankel (P-F))

Summary

Introduction

Flash memory cells are based on the floating gate technology principle [1]. The most widespread solution to enable semiconductor memories to be non-volatile, that is to say able to keep information without any power supply, is to use MOS transistors whose threshold voltage is shifted by a charge stored in an isolated gate above the channel. A. Floating-Gate test structure The Floating-Gate test structure, presented, consists in a large High-Voltage transistor whose gate is common with the Top Electrode of a large tunnel capacitor, denoted Ctun. Floating-Gate test structure The Floating-Gate test structure, presented, consists in a large High-Voltage transistor whose gate is common with the Top Electrode of a large tunnel capacitor, denoted Ctun This common gate plays the role of the Floating-Gate in a memory cell but is directly accessible to apply biases. Floating-Gate Technique methodology The Floating-Gate Technique (FGT) is based on the voltage measurement of an initially charged gate of a MOS capacitor, which is disconnected from the external circuit during the experiment The measurement of this slowly decreasing gate voltage is performed indirectly through the measurement of the drain current of the transistor sharing its gate with the capacitor. The improvement consists in developing a cheap but very sensitive test bench, embedded in a particular environment

Specific test environment

Relaxation model

Relaxation with Memory Effect

Curve fitting

Comments and discussions

Conclusion