Spatial and energetical profiles of defects extracted from ultra-low level trap-assisted leakage current in non-volatile floating thin tunnel oxide memory devices by using direct and floating gate technique measurements

Abstract

Stress induced leakage currents (SILC) remain one of the main reliability problems preventing further SiO 2 tunnel oxide thickness reduction in floating thin oxide (FLOTOX) memory devices. In this work, we present ultra-low level SILC current–voltage ( I– V) measurements performed by using the floating gate technique on 7–8 nm thick SiO 2 tunnel oxides and low-level measurements performed by direct technique measurements. Experimental characteristics obtained by the indirect measurement technique reached current levels as low as 2 × 10 −17 A. They exhibit new phenomena such as negative differential resistance behavior and current threshold voltages. A physical one-step tunneling model (A-mode), taking into account the influence of defects located in the bulk SiO 2, is proposed. Both spatial and energetical defect profiles are extracted from experimental data. We show that the new phenomena experimentally observed can be interpreted as a one step trap-assisted tunneling mechanism via defects located near the middle oxide, even for highly stressed components.