Floating-body Devices Research Articles

Defect characterization in floating body transistors using a single pulse charge pumping method

Field-effect transistors on a floating body channel have been used for a range of applications, such as three-dimensional nand flash and high-performance devices on silicon-on-insulator wafers. Conventional techniques to characterize the defect states cannot be implemented because those transistors do not have body contacts. A single-pulse charge pumping (SPCP) method was introduced to characterize the defect state distribution of the floating body transistors. The results extracted from the SPCP method on the three-terminal transistors (without body contact) agreed well with those from a conventional charge pumping method or SPCP on four-terminal transistors (with body contact). The validity of the SPCP measurement of the floating body devices was demonstrated by monitoring the increase in the defect state of the three-terminal poly-Si transistors density during the bias stress test. The SPCP method could detect the defect states of floating body transistors with high resolution.

Temperature dependence of single-event transient response in devices with selective-buried-oxide structure

The silicon-on-insulator (SOI) device has been found to possess low leakage current and high operation speed due to reduced internal capacitances. The sensitive volume for charge collection in SOI device is smaller than that in bulk-silicon device, which improves the ability of SOI devices to resist single-event effect (SEE). In spite of these benefits, the SOI device has certain undesirable effects such as the kink effect. To mitigate the kink effect, selective-buried-oxide (SELBOX) SOI structure has been introduced. Space-borne electronic circuits based on SOI technology recently have been used in high radiation and extreme temperature environments. However, temperature affects internal carrier transport process and impact ionization process, which makes single-event transient (SET) pulse widths increased. Most of previous researches regarding temperature dependence of SEE were for SOI floating-body devices. But the influence of operating temperature on SEE of SELBOX SOI devices are yet unclear. In this paper, an SOI floating-body device and a SELBOX SOI device under 90 nm process are established by three-dimensional device simulation, and then temperature dependence of SET response in partially depleted SOI inverter chains is studied by a mixed-mode approach over a temperature range from 200 K to 450 K. Simulation results show that the N-type SELBOX SOI device has a better ability to resist SEE than the floating-body device, while the P-type SELBOX SOI device has the same ability to resist SEE at high linear energy transfer value as the floating-body device. And temperature dependence analysis of charge collection indicates that there is only drift-diffusion process in the N-type SELBOX SOI device. The amount of charge collection in the N-type SELBOX SOI device almost does not change with the increase of temperature. In addition, both the P-type SELBOX SOI device and the P-type floating-body device have a bipolar amplification process. With the increase of temperature, the bipolar amplification process in the substrate turns more serious. However, it suppresses the bipolar amplification process of the source because of SELBOX structure, so that the amount of charge collection is reduced in the drain significantly. According to our simulation results, compared with the floating-body device, the SELBOX SOI device can very well suppress the influence of temperature on SET pulse.

Enhanced Radiation Hardness in SOI MOSFET with Embedded Tunnel Diode Layer

This paper presents an improved body tie structure for partially depleted silicon-on-insulator (SOI) MOSFETs. Inspired by tunneling current of degenerated p-n-junction at low forward bias, a tunnel diode layer is inserted at back channel forming a new type of body tie. The tunnel diode layer can be prepared either by ion implantation or in situ silicon deposition, which is fully compatible with present commercial SOI processes. The introduced body contact serves as an additional current flowing path for accumulated majority carriers generated by impact ionization or heavy-ion radiation, reducing critical floating body effects. The heavily doped tunnel diode layer extending from source to drain improves total dose radiation hardness and suppresses front-back channel coupling of SOI MOSFET for increasing back-gate threshold voltage and reduced width of space charge region. Experimental and simulation results validate the usefulness of the introduced body tie in enhancing radiation hardness of SOI transistor comparing with the conventional floating body devices. Therefore, SOI device with embedded tunnel diode layer can be considered as a promising candidate in spaceborne applications.

Operating Voltage Constraints in 45-nm SOI nMOSFETs and Cascode Cores

We investigate the operating voltage constraints and hot carrier reliability (HCR) of 45-nm SOI RF nMOSFETs and cascode cores built from these devices. The devices were implemented with both “floating” body and “contacted” body schemes. It is shown through experimental results that floating-body (FB) devices have greater hot carrier degradation compared with body-contacted (BC) devices. Cascode cores designed with two FB devices (FB-FB), with one BC device and one FB device (BC-FB), and with two BC devices (BC-BC), were also investigated. The tradeoffs in the dc versus radio-frequency (RF) performance versus the HCR of these cascode cores were assessed. The cascode cores have a much longer reliability lifetime compared with a single device operating under similar stress conditions. The BC-BC cascode core is shown to have a much longer reliability lifetime compared with BC-FB and FB-FB cascode core topologies. The physical mechanisms behind the observed hot carrier degradation in these devices and cascode cores are explored using calibrated technology computer-aided design (TCAD) simulations. Taken together, these results suggest some important implications for realizing high-performance and high-reliability RF circuit designs using 45-nm CMOS-on-SOI technology.

Improved Characterization Methodology of Gate-Bulk Leakage and Capacitance for Ultrathin Oxide Partially Depleted SOI Floating-Body CMOS

Device scaling of partially depleted (PD) silicon-on-insulator (SOI) has the potential to increase speed. However, the increased gate tunneling and capacitance will complicate device behaviors and increase the difficulty in characterization for modeling purpose. For the first time, gate-bulk leakage current Igb and gate capacitance Cgg characterization methodology for PD SOI floating-body (FB) CMOS with high accuracy is proposed and verified in 40-nm SOI devices. These devices are with ultrathin equivalent oxide thickness of 12A, and radio frequency-capacitance voltage (RF-CV) technique is used for Cgg measurement to overcome the impact of leaky gate current. This methodology can eliminate properly the parasitic elements due to the coexistence of opposite poly gate type in the SOI T-shape body-tied device and accurately characterize and model Igb and Cgg behaviors for the PD SOI FB devices. Test patterns are designed with RF ground-signal-ground configuration and same test patterns can be used for both Igb and Cgg characterization. Impact of Igb and Cgg changes on the history effect, and speed and body potential is analyzed by BSIMSOI4.0 models. Simulation accuracy of history effect will have at least 3% improvement with this proposed methodology.

A New Charge-Pumping Technique for a Double-Gated SOI MOSFET Using Pulsed Drain Current Transients

A novel interface characterization technique is proposed to extract interface trap density Nit in fully depleted silicon-on-insulator MOSFETs. The proposed technique utilizes the temporal variation of the drain current, which is caused by the application of a single pulse to the gate in order to trigger charge pumping (CP). Vacant interface traps created as a result of recombination through the CP effect are gradually filled by carriers generated from a floating body (FB). By the characterization of this transient phenomenon, the interface trap density is directly extracted from FB devices without extra body contacts.

An Extraction Method of the Energy Distribution of Interface Traps by an Optically Assisted Charge Pumping Technique

The energy distribution of interface traps is extracted using an optically assisted charge pumping (optical CP) technique. Optically generated majority carriers through light illumination enable the CP process even in a floating-body (FB) device without an extra body contact. With the use of square pulses at different rising and falling times and the proposed analytical model, the energy distribution of the interface traps is investigated via an optical CP technique. The optical CP technique is useful to extract the energy distribution of interface traps, as well as the interface-trap density in nanoscale FB devices. The data extracted by the optical CP is verified in a comparison with the data extracted by subthreshold-slope techniques.

Interface-Trap Analysis by an Optically Assisted Charge-Pumping Technique in a Floating-Body Device

An optically assisted charge-pumping (CP) technique is proposed for the characterization of interface traps in floating-body (FB) devices. Even without a body contact, majority carriers can be supplied into the FB by light illumination, which contributes to enabling the CP process. Under a strong inversion enabled by a back gate, the front gate triggers the CP process with a designed pulse waveform. Consequently, modulation of the majority-carrier concentration at the front interface is monitored by the change of the drain current. Thus, the interface-trap density is extracted from the monitored drain current and the developed analytical model.

Evaluating the Influence of Various Body-Contacting Schemes on Single Event Transients in 45-nm SOI CMOS

We investigate the single-event transient (SET) response of T-body and notched-body contacted MOSFETs from a commercial 45 nm SOI RF-CMOS technology. Although body-contacted devices suffer from reduced RF performance compared to floating body devices, previous work on 65 nm and 90 nm MOSFETs has shown that the presence of a body-contact significantly mitigates the total ionizing dose (TID) sensitivity that is exhibited in floating-body SOI MOSFETs. The influence of body-contacting schemes on the single-event effect (SEE) sensitivity is examined here through time-resolved measurements of laser and microbeam-induced transients from T-body and notched-body MOSFETs. Laser-induced transients demonstrate the reduced SEE sensitivity of the notched-body MOSFETs as compared to the T-body MOSFETs; this is evidenced by a uniform reduction in the peak transient magnitudes and collected charge for transients captured at the worst-case bias of VDS = 1.0 V, as well as with all terminals grounded. Microbeam-induced transient data are also presented to support the validity of the laser-induced transient data. Together, these data provide new insight into the RF versus TID versus SEE tradeoffs associated with body contacting schemes in nm-scale MOSFETs, an important concern for emerging space-based electronics applications.

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

A 7-dB 43-GHz CMOS Distributed Amplifier on High-Resistivity SOI Substrates

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (<formula formulatype="inline"><tex>${{\hbox{10}} \ \Omega \cdot {\hbox {cm}}}$</tex></formula>) or high-resistivity <formula formulatype="inline"><tex>$({&gt;}{\hbox{1 k}}\Omega \cdot {\hbox {cm}}$</tex> </formula>) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the impact of active device performance and transmission line losses on circuit design by means of simulations, analytical calculations, and comparisons of the small-signal equivalent-circuit parameters. On standard-resistivity substrates, DAs with FB devices and lossy microstrip lines on thin film exhibit a measured gain of 7.1 dB and a unity-gain bandwidth (UGB) of 27 GHz for a dc power consumption of 57 mW. With the introduction of high-resistivity substrates, other DAs, with the same architecture and using lower loss coplanar waveguide lines, show a UGB of 51 GHz with FB devices and 47 GHz with BC devices. To the authors' knowledge, the designs presented in this paper achieve the best tradeoffs in terms of gain, bandwidth, and power consumption for CMOS-based circuits with comparable architecture. </para>

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (Vg = Vd), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously (concurrent HCI-NBTI), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under Vg = Vd at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under Vg = Vd shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.

Total ionizing dose effects on deca-nanometer fully depleted SOI devices

Total ionizing dose effects are investigated for the first time in deca-nanometer fully depleted (FD) silicon-on-insulator (SOI) devices. Charge trapping and the influence of device architecture are investigated in transistors with and without external body contacts. A radiation-induced high current regime is measured in floating body devices, both at high and low drain voltages. The mechanism responsible for the onset of this high current regime is investigated by 2D numerical simulations, and shown to result from the combined effect of short gate length and floating body potential in the intrinsic Si film. Transistors with a doped Si film are less sensitive to the high current regime. The use of external body contact in the device architecture completely stops the onset of high current regime, whatever the device gate length.

Degradation of Low-Frequency Noise in Partially Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field-Effect Transistors by Hot-Carrier Stress

In this study, we determined the effects of hot-carrier stress on the low-frequency noise characteristics of partially depleted metal–oxide–semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator (SOI) technology. In devices with a floating-body configuration, kink-related excess noise was observed due to the floating-body effect. The level of this excess noise decreased after normal-mode stress, while it was masked by 1/ f noise after reverse-mode stress. The effects of stress-generated interface traps on the drain-to-body leakage current and the floating-body effect were also determined and used to explain the noise behavior. Moreover, the stress-induced 1/ f noise degradation in floating-body devices and body-contact devices was studied. It was found that the 1/ f degradation of body-contact devices is more significant than that of floating-body devices after hot-carrier stress.

Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures

The low-frequency noise characteristics of partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator technology at various temperatures were investigated. For floating-body devices, a Lorentzian-like noise overshoot is observed due to the floating-body effect. The noise overshoot is dependent on temperature and bias, and can be reduced using a source-to-body-connected structure. At high temperature or high drain bias, the 1/f noise will be observed, and it is temperature-independent due to the trap-induced mobility fluctuation in the channel.

Body charge modelling for accurate simulation of small-signal behaviour in floating body SOI

We show that careful modelling of body node elements in floating body PD-SOI MOSFET compact models is required in order to obtain accurate small-signal simulation results in the saturation region. The body network modifies the saturation output conductance of the device via the body–source transconductance, resulting in a pole/zero pair being introduced in the conductance–frequency response. We show that neglecting the presence of body charge in the saturation region can often yield inaccurate values for the body capacitances, which in turn can adversely affect the modelling of the output conductance above the pole/zero frequency. We conclude that the underlying cause of this problem is the use of separate models for the intrinsic and extrinsic capacitances. Finally, we present a simple saturation body charge model which can greatly improve small-signal simulation accuracy for floating body devices.

Analytical modeling of the partially-depleted SOI MOSFET

An analytical model for the partially-depleted (PD) silicon-on-insulator (SOI) MOSFET above threshold was developed. In contrast to previous models, this model includes front-back interface coupling with all the possibilities associated with it (accumulated, neutral, and depleted back interface). The model applies to tied-body as well as floating-body devices; however, thermal and edge effects are neglected. Interface coupling and floating-body effects are integrated together in a new "unified" algorithm. The "pseudo-two-dimensional" approach (which was used successfully to model lateral fields in bulk-Si devices) is extended to SOI devices. The model is extremely physical and thus highly predictive. Good agreement with experiment was obtained over a wide range of channel lengths and back gate voltages. Because of the model's neglect of thermal effects, however, disagreement was observed at high current levels. A brief physical interpretation of the results is also presented.

Three-dimensional modeling and evaluation of body tied versus floating body SOI MOSFETs

A computationally efficient and suitable device model has been determined and applied for three-dimensional (3-D) modeling and evaluation of body tied versus floating body SOI MOSFETs. Quarter micron Partially-Depleted (PD) devices have been considered. The transistor characteristics for the devices have been generated from 3-D device simulations, allowing evaluation of the influence of body ties on floating body effects in PD devices. By overcoming the convergence difficulties encountered in numerical solutions when dealing with floating body problems, the kink occurring in the saturation region of the output current–voltage characteristics of the floating body device, and its reduction and suppression in the devices with various body tie configurations has been determined. The results presented appear to be the first reported attempt at determining the influence of body ties on the kink effect from determination of the output current–voltage characteristics directly obtained from 3-D device simulations. Only DC type floating body effects have been considered in this work.

Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies. >