Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

Abstract

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies. >