BiMOS modeling for reliable SOI circuit design

Abstract

Summary form only given. Recent work has clearly revealed that transient current in the parasitic bipolar junction transistor (BJT) of the floating-body SOI MOSFET can be significant and degrading even in SOI circuits operating at voltages well below the BJT-defined drain-source breakdown. The BJT is also critically important with regard to soft errors in low-voltage SOI memory circuits. In these cases, the BJT current is driven by dynamic charging of the body and concomitant forward biasing of the source (or drain) junction, supported by capacitive, or charge coupling between the BJT and the MOSFET. A reliable circuit model for the floating-body SOI MOSFET must therefore account for the coupled BJT. In this paper we present a new, quasi-2D parasitic BJT model physically coupled to the SOISPICE MOSFET models and defined in terms of their parameters. We further use physical insight derived from this BiMOS modeling to identify a new means of controlling the transient BJT, or leakage current in SOI MOSFETs which could be exploited in design.