Flip-flop Output Research Articles

An Experimental Study of Metastability-Induced Glitching Behavior

The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [Formula: see text] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.

A Low-Power Three-Tap DFE with Switched Resistor Slicer and CTLE in 0.18μm CMOS Technology

In this paper, a switched resistor slicer is proposed to reduce the power consumption of a decision feedback equalizer (DFE). In the proposed structure, summer circuit that consumes most of the power in a DFE has been eliminated and proper resistors are added as the load of a slicer based on a flip-flop output bit stream. Incorporating the proposed DFE circuit with continuous time linear equalizer (CTLE) at the serial link receiver over a 1[Formula: see text]m NELCO (the NELCO[Formula: see text] N4000-13 series is an enhanced epoxy resin system engineered to provide both outstanding thermal and high signal speed/low signal loss properties) channel can compensate 24[Formula: see text]dB loss at the Nyquist frequency of 2[Formula: see text]GHz. CTLE is adjusted to compensate 6[Formula: see text]dB of channel loss which remains after utilizing a DFE with three taps. The proposed structure has been designed in 0.18[Formula: see text][Formula: see text]m CMOS technology while consuming 13.5[Formula: see text]mW from 1.8[Formula: see text]V supply at 4[Formula: see text]Gb/s with a bit error rate less than 10[Formula: see text]. The proposed equalizer power consumption is reduced by 43% compared to the conventional circuit.

Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits

This brief presents a high-speed inductorless D flip-flop (DFF) architecture that works on the principle of equalization using two feedbacks. Feedback from the first latch output to the input effectively results in a linear equalizer, whereas the feedback of the flip-flop output to the input culminates in decision feedback equalization. The proposed feedback-based DFF designed in a 90-nm CMOS technology shows 37.5% improvement in speed, as compared with the conventional flip-flops (conv-DFFs) without feedbacks. Post-layout circuit simulations also show an overall 33.7% improvement in the speed of a high-speed pseudorandom binary sequence generator when such feedbacks are added to conv-DFFs in it. Additionally, when this technique is used in a Hogge phase detector for clock and data recovery, 89% improvement in vertical eye opening and 73% reduction in pattern-dependent jitter at the input of the phase detector are observed. In essence, the technique effectively achieves distributed equalization in high-speed communication circuits.

A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells

In this work, a zero-leakage nonvolatile flip-flop architecture based on a differential CMOS sense-amplifier flip-flop is presented. The flip-flop stores data in complimentarily programmed resistive memory devices during inactive period while power supply is turned off and then restores the data to flip-flop outputs once power supply is turned back on. The resistive memory technology considered here are known as programmable metallization cell (PMC) that switches via metal ion transport within a solid electrolyte. Simulations of the proposed circuit using a PMC compact model fitted to experimental data are performed to estimate the reliability of the read operation and energy consumption for both nominal and sub-threshold power supply regimes. Energy and reliability tradeoffs in the choice of the programmable low resistance state are also discussed. The proposed sense amplifier- based design is more compact than previously reported master-slave latch based nonvolatile designs and presents a modified data restore circuit for more robust read operation at subthreshold voltage supply levels. The wide margin between high and low resistance states of the PMC devices further improves robustness of the flip-flop. Lastly, possible extension of this architecture for low power logic computation application is briefly discussed.

A New High Resolution Measurement Technology of D Flip-Flop Output Signals for Measuring Frequency Difference

The output periods of D flip-flop mixer are variable though the periods of two input frequencies are invariable. To measure the output frequency, the conventional method is to calculate the average value of the output periods and the maximum possible absolute error is a clock period. The variation of the output periods has its own pattern of arrangement and it can provide valuable information. Measuring accuracy can be significantly improved by taking into account all the details of output periods changes. A mathematical model that describes the relationship between the input square waves and the output square waves was developed and the difference of two input frequencies can be estimated by the solution of the model. The new method is quite suitable for measuring small frequency increments of quartz crystal resonators.

AC-Plus Scan Methodology for Small Delay Testing and Characterization

Small delay defects escaping traditional delay testing could cause a device to malfunction in the field and thus detecting these defects is often necessary. To address this issue, we propose three test modes in a new methodology called AC-plus scan, in which versatile test clocks can be generated on the chip by embedding an all-digital phase-locked loop (ADPLL) into the circuit under test (CUT). AC-plus scan can be executed on an in-house wireless test platform called HOY system. The first test mode of our AC-plus scan provides a more efficient way to measure the longest path delay associated with each test pattern. Experimental result shows that our method could greatly reduce the test time by 81.8%. The second test mode is designed for volume production test. It could effectively detect small delay defects and provide fast characterization on those defective chips for further processing. This mode could be used to help predict which chips are more likely to fall victim to operational failure in the field. The third test mode is to extract the waveform of each flip-flop's output in a real chip. This is made possible by taking advantage of the almost unlimited test memory our HOY test platform provides, so that we could easily store a great volume of data and reconstruct the waveform for post-silicon debugging. We have successfully fabricated a Viterbi decoder chip with such an AC-plus scan methodology inside to demonstrate its capability.

Elimination of output gating performance overhead for critical paths in scan test

Excessive switching activity in test mode results in higher power dissipation than normal mode of operation and becoming a serious issue, in order to avoid reliability problems. Scanning of test vectors in test mode causes unnecessary switching in combinational block which can be reduced by gating methods. Gating the outputs of scan cells is a recently proposed very efficient low power test technique, which reduces the scan shift power significantly. However, the output gating techniques impacts the performance severely. In this paper, we propose a modified transistor level design of a scan flip-flop for critical paths, which eliminates the unnecessary switching in combinational circuit during shift phase of a scan-based test, without the impact on performance as in earlier scan flip-flop output gating schemes (Khatri and Ganeshan, 2008). The new scan flop design not only eliminates the performance overhead of output gating but also improves the performance of the scan flop by 32.84% (Khatri and Ganeshan, 2008) and 11.5% (Yang et al., 2008). The new flip-flop disables the output and uses an alternate path for shifting the test vectors. This approach have area overhead of six extra transistors but improves the overall performance of scan flip-flop, so this approach is better suited for critical paths. This also allows us to increase the shift frequency in designs where shift power dissipation puts upper bound on the frequency, and hence reduces test application time.

All-optical flip-flop memory using SOA-based modelocked ring lasers with optical feedback

An all-optical flip-flop memory is built-up based on two ring lasers, where a semiconductor optical amplifier (SOA) is shared in two laser cavities. The flip-flop outputs short pulses that have tunable central wavelengths, a pulsewidth of 1.5 ps (FWHM) at 10 GHz, generated by actively modelocking using phase modulation. Bistability of the flip-flop is observed by introducing optical feedback via an external cavity. The static contrast ratio of the device is over 20 dB between the dominating and suppressed states and the switching power is as low as 18 dBm.

20 ps Transition Time All-Optical SOA-Based Flip-Flop Used for Photonic 10 Gb/s Switching Operation Without Any Bit Loss

A novel scheme for integrable ultrafast all-optical flip- flop is demonstrated. Transition times as low as 20 ps with a contrast ratio higher than 17.5 dB have been experimentally measured. All-optical switching operation in a 2times2 spatial and wavelength preserving switch is reported with a power penalty of about 1 dB. The proposed solution exploits the fast falling edge provided by a semiconductor optical amplifier (SOA) based optical flip-flop. Numerical investigations already demonstrated high extinction ratios (>40 dB) and low switching energies (15.6 fj) for integrated optical flip-flop. On the other hand, slow rising times, due to the cavity length, intrinsically limit such configurations. By using SOA-based logic gates, two flip-flop outputs are combined in a new bistable signal. Both the new rising and falling edges are related to the primary flip-flop falling edge. This way it is possible to eliminate the intrinsic slow rising time that limits the flip-flop configuration based on the coupled ring lasers, without excessively increasing the complexity of the structure and maintaining a reasonably high contrast ratio. Furthermore, the noise on the high level has been improved due to the regenerative properties of the logic gates based on cross-gain modulation and cross-phase modulation in a single nonlinear SOA. Finally, flip-flop output has been used to drive a 2times2 all-optical spatial and wavelength preserving switch based on SOAs. For cross/bar switch configurations, 10 Gb/s error-free operation has been obtained without bit loss.

Ultrafast All-Optical Wavelength Routing of Data Packets Utilizing an SOA-Based Wavelength Converter and a Monolithically Integrated Optical Flip–Flop

We demonstrate all-optical wavelength routing of 80 Gb/s data packets without using electronic control. The system consists of an optical wavelength converter and a monolithically integrated optical flip-flop memory. The integrated optical flip-flop is based on two coupled lasers, exhibiting single-mode operation, having a 35 dB contrast ratio between the states, and switching its state in about 2 ns. The wavelength converter is optically controlled by the optical flip-flop. We show that the optical set and reset pulses can force the optical flip-flop to switch its continuous-wave output light between two specific wavelength positions. The output light feeds the wavelength converter, which, in turn, converts the data packet into the flip-flop's output wavelength, causing the data packet to be routed into a specific port.

Multiple-output low-power linear feedback shift register design

In this paper, we present a new low-power architecture for linear feedback shift registers (LFSRs) that produces the output of several clock cycles of a serial LFSR at once while reducing the activity factors of the flip-flop outputs. The frequency of operation can thus be reduced by a factor equal to the number of outputs produced at a time. A reduction in the frequency of the LFSR allows for a reduction in the power-supply voltage. Thus, dynamic power dissipation is reduced by up to 93% due to decreases in power-supply voltage, frequency, and the activity factor. Furthermore, the hardware needed for our implementation is far less than previous low-power implementations of both single and multiple-output LFSRs. Our method is also good for built-in self-test (BIST) applications because for most degrees of N it results in all 2/sup N/-1 distinct patterns.

Metastability tests of flip–flops in programmable digital circuits

This paper describes the methods and experimental techniques for determination of the metastability behavior of the flip–flops used in the programmable digital circuits. A dual model of the metastability distinguishes two transitions at the flip–flop output (L/H and H/L) which have different impact on the Mean Time Between Failures (MTBF) of the flip–flop. A new circuit of the late transition detector (LTD) allows for determination of the pairs of the metastability parameters, the window W and the time constant τ, for both transitions. The test results are presented for four types of programmable digital circuits fabricated commercially in CMOS technology. In the all tests, the H/L transition clearly dominates with respect to MTBF (as a worse one). The presented test methods can also be used for evaluation of flip–flops in nonprogrammable digital circuits.

Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis--A Genetic Algorithm Approach

This paper presents a genetic algorithm (GA)-based approach for the synthesis of a finite state machine (FSM). Three aspects---state assignment, choice of polarity for the state bits and the polarities of the primary outputs---significantly affect the cost of the combinational logic synthesized for an FSM. Thus, the problems of state assignment, flip-flop polarity selection and output polarity selection have been integrated into a single genetic algorithmic formulation. The experiments performed on a large suite of benchmarks have established the fact that this tool outperforms the existing two-level state assignment algorithms. The quality of the solution obtained and the high rate of convergence have established the effectiveness of the GA in solving this difficult problem.

Switched Flip-Flop based Preprocessing Circuit for ISFETs

In this paper, a preprocessing circuit for ISFETs (Ion-sensitive field-effect transistors) to measure hydrogen-ion concentration in electrolyte is presented. A modified flip-flop is the main part of the circuit. The modification consists in replacing the standard transistors by ISFETs and periodically switching the supply voltage on and off. Concentration of hydrogen ions to be measured discontinues the flip-flop value symmetry, which means that by switching the supply voltage on the flip-flop goes to one of two stable states, ‘one’ or ‘zero’. The recovery of the value symmetry can be achieved by changing a balanced voltage, which is incorporated to the flip-flop, to bring the flip-flop to a 50% position (probability of ‘one’ equals to probability of ‘zero’). Thus, the balanced voltage reflects the measured concentration of hydrogen ions. Its magnitude is set automatically by using a feedback circuit whose input is connected to the flip-flop output. The preprocessing circuit, as the whole, is the well-known Δ modulator in which the switched flip-flop serves as a comparator and a sampling circuit. The advantages of this approach in comparison to those of standard approaches are discussed. Finally, theoretical results are verified by simulations with TSPICE and a good agreement is reported.

Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults

We propose a possible modification to the internal structure of scan flip-flops, which allows the online detection of delay and crosstalk faults affecting their input. Our solution allows to obtain, together with the flip-flop output datum, an indication denoting whether or not the provided datum is incorrect, because of an input crosstalk or delay fault. The proposed solution features self-checking ability with respect to a wide set of possible internal faults, including node stuck-ats, transistor stuck-ons and stuck-opens, resistive bridgings, delays, transient and crosstalk faults.

Estimation of state line statistics in sequential circuits

In this article, we present a simulation-based technique for estimation of signal statistics (switching activity and signal probability) at the flip-flop output nodes (state signals) of a general sequential circuit. Apart from providing an estimate of the power consumed by the flip-flops, this information is needed for calculating power in the combinational portion of the circuit. The statistics are computed by collecting samples obtained from fast RTL simulation of the circuit under input sequences that are either randomly generated or independently selected from user-specified pattern sets. An important advantage of this approach is that the desired accuracy can be specified up front by the user; with some approximation, the algorithm iterates until the specified accuracy is achieved. This approach has been implemented and tested on a number of sequential circuits and has been shown to handle very large sequential circuits that can not be handled by other existing methods, while using a reasonable amount of CPU time and memory (the circuit s38584.1, with 1426 flip-flops, can be analyzed in about 10 minutes).

Improving the detection limit of a quadrupole mass spectrometer

First Page

On Non-Statistical Techniques for Fast Fault Coverage Estimation

We present fast, dynamic fault coverage estimation techniques for sequential circuits that achieve high degrees of accuracy and significant reductions in the number of injected faults and faulty-event evaluations. In the proposed techniques, we dynamically reduce injection of hyperactive faults as well as faults whose effects never propagate to a flip-flop or primary output. Suppression and over-specification of potential fault-effects are also investigated to reduce faulty-event evaluations. Experiments show that our methods give very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed techniques can be combined with the sampling approach to obtain speedups comparable to small sample sizes and retain estimation accuracy of large fault samples.

RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER

Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.

Upset due to a single particle caused propagated transient in a bulk CMOS microprocessor

Data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one of the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N/sub 2/ gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LETs, a 24-26 MeV-cm/sup 2//mg LET threshold was deduced. Subsequent cyclotron tests established an LET threshold of 30 MeV-cm/sup 2//mg (283 MeV Cu at 0 degrees ) for the generation of false clocks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>