Flip-chip Bump Research Articles

A comparative study on direct Cu–Cu bonding methodologies for copper pillar bumped flip-chips

Copper pillar micro bump is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking and high-density electronic components. In this study, Cu–Cu direct thermo-compression bonding (TCB) and anisotropic conductive paste (ACP) bonding methods are proposed for O 100 µm Cu-pillar bumped flip-chips. The process parameters including bonding temperature, bonding pressure and time are verified by die shear test and SEM/EDX cross-sectional analysis. The optimal bonding condition for TCB with regards to bonding pressure was defined to be 0.5N/bump at 300 °C or 0.3N/bump at 360 °C. In the case of ACP bonding, the minimum bonding pressure was about 0.3N/bump for gaining a seamless bonding interface.

Lead-free solder wettability of oxidized-aluminum enhanced by Ar-H2 plasmas for flip-chip bumping

PurposeAn investigation has been performed on the improved solder wettability of oxidized aluminum (Al) with lead-free solder (96.5Sn-3.5Ag) using Ar-H2 plasmas. The lead-free solder wettability was raised from 62.2 per cent wetting for Al oxidized in air at 250 C for 4 h to 98.4 per cent wetting of oxidized Al modified by Ar-H2 plasmas at a certain H2 flow rate. This study aims to gain insight on the surface characteristics of Al affecting the solder wettability with a liquid lead-free solder.Design/methodology/approachAr-H2 plasmas at certain H2 flow rates are intended to reduce Al oxides on the surfaces of oxidized Al substrates both by physical bombardments via Ar plasmas and chemical reductions with H2 plasmas, while Al substrates are exposed in Ar-H2 plasmas to improve the solder wettability with a liquid lead-free solder.FindingsSurface characteristics of oxidized Al substrates have been identified to play key roles for enhanced lead-free solder wettability using Ar-H2 plasmas. A decrease in polar surface free energy and an increase in dispersive surface free energy on the surfaces of oxidized Al substrates are exploited to advance the lead-free solder wettability. Decreased composition ratios of O to Al, detected by X-ray photoelectron spectroscopy (XPS) for oxidized Al substrates, are crucial for improved lead-free solder wettability.Originality/valueXPS is typically used to analyze the surface compositions of Al oxides. To provide a rapid and non-expansive method to identify the surfaces of Al substrates prior to soldering to assure lead-free solder wettability, this study proposes a measurable skill, a so-called sessile drop test method, to investigate surface free energies such as total, polar and dispersive surface free energy on the surfaces of Al substrates, to illuminate how the lead-free solder wettability of oxidized Al is improved by Ar-H2 plasmas.

Design of Experiments Approach to Evaluating the Reliability of System-in-Package Assemblies

Abstract Reliability in microelectronic packaging has been, and will continue to be, a major concern that must be taken into account early in the design of a package. System-in-package (SiP) assemblies, as well as other high density packaging technologies, are being used in many system architectures in order to incorporate a high level of integration, reduce cost and fit on tighter next higher assembly (NHA) grid spacing. While these technologies are being adopted into system architectures, there is limited test data on the reliability of these packages in military applications. A better understanding of the impacts of design variables in a SiP assembly allows the design community to determine the most appropriate packaging solution for use in a given application. The term “system-in-package” covers a wide range of microelectronic packaging technologies. Microelectronic packaging technology is trending towards taking the SiP concept and incorporating a very high level of integration within as small of a footprint as possible. In many cases, a fan out design technique is used in order to utilize die with high density bump patterns and then use an interposer technology to increase the bump pitch to match pitches achievable on NHA board technologies. While increasing the packaging density appears beneficial in theory, its reliability becomes a risk as the complexity of the assembly increases and more interfaces are added. Mechanical and structural considerations must be taken into account when designing this type of assembly in order to limit the stresses observed in the assembly, especially when exposed to environmental conditions. This study will focus on traditional two dimensional (2D) integrated circuit (IC) designs. For the purposes of this study, a 2D IC package will be considered as multiple die attached to a SiP substrate via flip-chip bumps. These SiP assemblies will in turn be attached to a test circuit board via solder bumps, which are at a larger pitch relative to the flip-chip bump patterns. A daisy-chain circuit design was incorporated into the test board and die in order to evaluate the reliability of the assembly interconnects at various points throughout the assembly. Design variables such as underfill material, SiP substrate material and flip-chip bump density were incorporated into a design of experiments in order to evaluate their impact on the reliability of a SiP assembly. The materials selected for use in this testing allow for the evaluation of the impacts of coefficient of thermal expansion (CTE), modulus and other material properties on the reliability of a SiP assembly. Reliability of the assemblies was tested via temperature cycling and biased humidity testing. Successful reliability of each test was dictated by the continuity of the daisy chain circuits throughout testing, as well as a visual examination of the interconnects after test. Samples of each assembly design configuration were used in cross sectional analysis to further examine the effects of the reliability on the assembly. Material characterization techniques such as scanning electron microscopy (SEM) and focus ion beam scanning electron microscopy (FIB-SEM) were used, as necessary, to investigate failure modes. This paper will review a design of experiments study of SiP assemblies and present the results of reliability testing on various SiP assembly designs. Further study is suggested for the use of these results in developing and refining finite element models capable of accurately predicting failure modes in SiP assemblies.

Die Placement Error management for Fan out Applications using Projection Lithography

Abstract Photolithography has long been the key patterning technology for structuring organic materials used in advanced packaging applications like flip-chip wafer bumping, electroplated gold, solder bumps, copper pillar technologies and redistribution layers. Photolithography is a key manufacturing process and cost contributor, the careful selection of the right exposure solution is critical to achieve the best possible cost structure in today's industrial lithography applications We will introduce a projection exposure technology that uses a 1:1 projection lens; the projection exposure technology provides high resolution patterning performance. With the capability of varying NA from 0.07 to 0.14, a large depth of focus is obtained, that is required to ensure high pattern fidelity when working with thick resists. The projection exposure can also be applied to FOWLP applications, when the die placement data is fed into a software optimization algorithm to correct for it. We will present the projection exposure technology capability in managing the die placement error for FOWLP. In addition, details on the overlay capability of the projection exposure in thin resist are described and a Cost-of-Ownership comparison between different photolithography solutions is discussed.

Shear test on hard coated flip-chip bumps to measure back end of the line stack reliability

Introduction of ultra-low κ (ULK) material into advanced back end of line (BEOL) stacks has improved the electrical performance of the flip-chip microelectronic packages. However, the integration of the brittle and porous ULK materials presents several mechanical reliability challenges due to chip-package interaction effects. One of the primary failure modes in a organic flip-chip microelectronic package is delamination of interlayer dielectric (ILD) layers. Thermo-mechanical stresses that arise at the end of flip-chip assembly process can be high enough to cause fracture of the ILD layers in the vicinity of a solder bump. It has been observed from experiments that two bumps subjected to apparently same amount of thermo-mechanical stresses and same process history can exhibit difference in failure pattern. Current numerical models nor micro- scale interfacial fracture characterization experiments such as double cantilever beam (DCB) or four-point bend (FPB) tests are not capable of predicting such a failure. Such a behavior is possible only if the adhesion strength of the ILD layers are not constant but varies spatially from bump to bump. The difference in adhesion strength between adjacent bumps can be attributed to the difference in trace pattern layout or via distribution. In order to understand the failure at the bump level that is sensitive to capture differences in local trace patterns, microscale test techniques need to be developed.The focus of this work is to demonstrate a new reliable microscale test technique performed using nano-indenter to measure the mechanical reliability of BEOL stacks. A high-load spherical head is used to apply a known displacement on a solder bump coated with a ceramic. The force initial increases and suddenly drops indicating failure. Cross-sections of the tested bumps clearly indicate crack propagating through the BEOL stack while the coated bump remains intact. Since the forces subjected on the bump during the test is similar to the forces subjected on the bump during flip-chip assembly, the critical force can be used as a measure of fracture strength of the BEOL stack. The results from the test indicate that the critical force varies from bump to bump and the results are repeatable. Furthermore, finite-element model of the test is developed. The failure of the ILD layers is simulated using cohesive zone (CZ) elements and the mixed-mode traction-separation parameters required to characterize the CZ elements are extracted from macro-scale test techniques like DCB and FPB tests. The force-displacement (P-Δ) plot from the model mimics the experiment and predicts the average value of the critical force observed in experiment.

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

Moisture Effects on NCF Adhesion and Solder Joint Reliability of Chip-on-Board Assembly Using Cu Pillar/Sn–Ag Microbump

Electronic devices as well as electronic packaging technology have required higher speed, I/O capability, and density. To meet these requirements, flip-chip solder bumps interconnection combined with reflow assembly process has been a widely used. In spite of the many advantages of flip-chip solder bump joints, there is a limitation for less than 100 $\mu \text{m}$ fine pitch interconnection due to the solder bump bridging during the assembly process. Therefore, nonconductive films (NCFs) and Cu pillar/Sn–Ag microbump interconnection become a promising interconnection solution for fine pitch assembly. However, NCFs technology has some problems for flip-chip assembly. Epoxy-based NCF can easily absorb moisture, causing delamination reliability problem at moisture environment. In order to solve the interconnection, the NCF adhesion should be enhanced. Silane coupling agent (SCA) was added to NCFs to secure the microbump joint reliability for chip-on-board assembly by increasing the adhesion strength in the pressure cooker test. After the humidity test, the NCFs’ modulus and Tg were increased by adding SCA content. Moreover, the measured adhesion strength and energy showed similar results after the humidity test that higher SCA content showed high adhesion strength and energy than lower SCA content and unmodified NCF at the interface between NCF and solder resist of the printed circuit board substrate. The bump joint lifetime of 5wt% SCA NCF was longer than 1wt% SCA and unmodified NCF after the humidity test. In this paper, we report results of our investigations on effects of employing SCA in NCF composition for improved moisture resistance.

The Bonding Forming Simulation and Reliability Research of the Flip-Chip Stacked Gold Stud Bump

The finite element model of the bonding forming for 3-D flip-chip stacked gold stud bumps was set up, and the bonding process of stacked gold stud bump was simulated by controlling the bonding conditions of pressure, power, and time. Then, the height and diameter of stacked gold stud bumps with 16 groups of different bonding parameter level combinations designed by the orthogonal experiment method were obtained by simulation of the model, and the simulation data were processed using the range analysis and the variance analysis. Samples corresponding to the above 16 groups of different bonding parameter level combinations were made and had a thermal cyclic loading experiment for reliability analysis. The results are shown as follows: The bonding pressure has the largest effect on the height and diameter of stacked gold stud bump, less effect on bonding power, and the least effect on bonding time; the bonding pressure has a significant effect on the height and diameter of stacked gold stud bump with 95% confidence, but does not have on the bonding power and time.

Effects of the degradation of methane sulfonic acid electrolyte on the collapse failure of Sn–Ag alloy solders for flip-chip interconnections

The degradation mechanism of the methanesulfonic acid based electroplating bath used for the electrodeposition of Sn–Ag alloy solder bumps and its effects on the collapse failure of flip-chip solder bumps.

Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package

Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package

Thermal warpage measurement system for environmental test of automotive devices

As automotive semiconductor market has expanded, the importance of measurement of temperature-dependent warpage (thermal warpage) has been increasing. For automobiles, high reliability is necessarily demanded because their failures are directly linked to people's life. Therefore automotive industry had established AEC qualification standards for automotive devices. The standard demands environmental tests that include not only high temperature test but also negative temperature test reaching -55 ℃. In view of this situation, we have developed a thermal warpage measurement system that has the ability to change sample temperature from -60 to 260 ℃ which can meet the demands of the standard. The following are some features of the system. <(1)Warpage measurement ability>Measurement is performed by confocal method which is well known as accurate optical metrology. Generally speaking, confocal method is time consuming method for measurement. But our technique we call non-scanning confocal method overcomes such a drawback maintaining advantages of confocal method and the non-scanning confocal method has already been used widely for in-line coplanarity inspection of flip-chip bumps. Conventional warpage measurement technique like Moire method needs sample preparation like de-ball and painting. But the non-scanning confocal method doesn”™t need any sample preparation. The method can measure not only substrate warpage accurately without de-ball but even ball height/coplanarity. Moreover the system can deal with even several tens of micron diameter bumps, because it has 8.0um pixel resolution regardless of sample size. Unlike conventional warpage measurement system, the field of view (FOV) size of 13x13mm is constant and bigger samples than the FOV can be measured by stitching FOVs using a XY translation stage up to 136x323mm (JEDEC tray size).<(2)Heating and cooling ability>The system has a big size chamber for heating and cooling so that a whole JEDEC tray can be measured. In order to heat all samples in the big chamber uniformly, convection heating is used as heating method. Convection heating has many advantages compared to radiation heating that is normally used by conventional systems. The advantages are as follows.

Application of robust color composite fringe in flip-chip solder bump 3-D measurement

This study developed a 3-D measurement system based on flip-chip solder bump, used fringes with different modulation intensities in color channels, in order to produce color composite fringe with robustness, and proposed a multi-channel composite phase unwrapping algorithm, which uses fringe modulation weights of different channels to recombine the phase information for better measurement accuracy and stability. The experimental results showed that the average measurement accuracy is 0.43μm and the standard deviation is 1.38µm. The results thus proved that the proposed 3-D measurement system is effective in measuring a plane with a height of 50μm. In the flip-chip solder bump measuring experiment, different fringe modulation configurations were tested to overcome the problem of reflective coefficient between the flip-chip base board and the solder bump. The proposed system has a good measurement results and robust stability in the solder bump measurement, and can be used for the measurement of 3-D information for micron flip-chip solder bump application.

On the Way from Fan-out Wafer to Fan-out Panel Level Packaging

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

Effects of Silicon Wafer Bump Pad Structures on Solder and Cu Pillar Flip-Chip Reliability

Abstract Solder and Cu pillar flip-chip silicon die technologies have been widely used in chip to package mobile module products. During the early design phase, integrated circuit (IC) designers usually apply standard bump design rules, due to lack of information on the reliability of the metal layer stack-up with different bumping processes. However, module reliability data has demonstrated that the stack-up and thickness of the metal layers in a silicon die has a great effect on package stresses, especially for large area Cu pillar flip chip die. In this paper, the effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly in-line data was collected and analyzed, and is presented in this paper. Reliability testing and failure analysis were performed to verify the failure modes. Guidelines for designing solder and Cu Pillar Flip-chip bump pad structures have been developed, and are presented in this paper.

Application of laser deprocessing technique in PFA on chemical over-etched on bond-pad issue

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC)11Integrated Circuit (IC). design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology.When come to PFA22Physical Failure Analysis (PFA). on the flip-chip devices with solder bump, wet etch for solder bump removal is an essential method. Upon using wet etch methodology; it is very dependent on etching timing and the chemical aggressiveness to get a good removal result for the solder bump. If there is an excessive period in etching or chemical reacts too aggressively, chemical over-etched on bond pad will occur. It is very unfavorable for FA33Failure Analysis (FA). engineer to perform subsequent reverse engineering on the bond pad over-etched device.In this paper, the application of laser deprocessing technique is proposed to solve the bond pad over-etched issue. This proposed technique is a quick and reversal way in deprocessing technique for defect identification in PFA.

The size effect on intermetallic microstructure evolution of critical solder joints for flip chip assemblies

Purpose – The purpose of this paper is to study the intermetallic compound (IMC) thickness, composition and morphology in 100-μm pitch and 200-μm pitch Sn–Ag–Cu (SAC305) flip-chip assemblies after bump reflow and assembly reflow. In particular, emphasis is placed on the effect of solder joint size on the interfacial IMCs between metal pads and solder matrix. Design/methodology/approach – This work uses 100-μm pitch and 200-μm pitch silicon flip chips with nickel (Ni) pads and stand-off height of approximately 45 and 90 μm, respectively, assembled on substrates with copper (Cu) pads. The IMCs evolution in solder joints was investigated during reflow by using 100- and 200-μm pitch flip-chip assemblies. Findings – After bump reflow, the joints size controls the IMC composition and dominant IMC type as well as IMC thickness and also influences the dominant IMC morphology. After assembly reflow, the cross-reaction of the pad metallurgies promotes the dominant IMC transformation and shape coarsened on the Ni pad interface for smaller joints and promotes a great number of new dominate IMC growth on the Ni pad interface in larger joints. On the Cu pad interface, many small voids formed in the IMC in larger joints, but were not observed in smaller joints, combined with the drawing of the IMC growth process. Originality/value – With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 to150 μm. This work shows that as the packaging size reduced with the solder joint interconnection, the solder size becomes an important factor in the intermetallic composition as well as morphology and thickness after reflow.

Formation of octahedral corrosion products in Sn–Ag flip chip solder bump

We investigated the corrosion behavior of the Sn–2.3wt.%Ag flip-chip solder bump in distilled water. At the early stage, dendritic corrosion products were converted into pyramidal shapes. The six pyramids grew simultaneously during a prolonged corrosion process. Finally, the octahedral corrosion products are formed. The octahedral corrosion product consisted of Sn and O, and was a mixture of amorphous and nanocrystalline SnO2 phase. The mechanism of this corrosion product was essentially a galvanic cell reaction.

Enhanced lead-free solder wettability of oxidized-nickel by Ar–H2 plasmas for flip chip bumping

Solder wettability (SW) of oxidized-nickel (ON) with liquid lead-free solder (LFS) (96.5Sn–3.5Ag) is notably improved by Ar–H2 plasmas from 0 % wetting of nickel substrate oxidized in air gases at 200 °C for 2 h to 100 % wetting of ON substrate treated by Ar–H2 plasmas at certain plasma settings. The SW of ON substrates with LFS is dependent on the surface characteristics of ON substrates. The enhanced SW of ON substrates with LFS by Ar–H2 plasmas is mostly due to a decrease in polar surface free energy and an increase in dispersive surface free energy on the surfaces of ON substrates. The ratios of the compositions of O to Ni are critical to the SW of ON substrate with LFS. The atomic compositions of Ni and O on ON substrates are analyzed by an energy-dispersive X-ray spectroscope. The nickel oxides NiO and Ni2O3 on the surfaces of ON substrate are identified by an X-ray photoelectron spectroscope.

New Failure Mode of Flip-Chip Solder Joints Related to the Metallization of an Organic Substrate

We report a new failure phenomenon during flip-chip die attach. After reflow, flip-chip bumps were separated between the Al and Ti layers on the Si die side. This was mainly observed at the Si die corner. Transmission electron microscopy images revealed corrosion of the Al layer at the edge of the solder bump metallization. The corrosion at the metallization edge exhibited a notch shape with high stress concentration factor. The organic substrate had Cu metallization with an organic solderable preservative (OSP) coating layer, where a small amount of Cl ions were detected. A solder bump separation mechanism is suggested based on the reaction between Al and Cl, related to the flow of soldering flux. During reflow, the flux will dissolve the Cl-containing OSP layer and flow up to the Al layer on the Si die side. Then, the Cl-dissolved flux will actively react with Al, forming AlCl3. During cooling, solder bumps at the Si die corner will separate through the location of Al corrosion. This demonstrated that the chemistry of the substrate metallization can affect the thermomechanical reliability of flip-chip solder joints.

Ultralow Residue (ULR) Semiconductor Grade Fluxes for Flip-Chip and MEMs Applications

Copper pillars topped with solder microbumps are emerging as a standard flip-chip solder bump replacement in the semiconductor assembly industry. The relentless drive towards finer pitch, combined with reduced copper pillar height, makes aqueous cleaning of flip-chip flux residues more difficult. An emergent failure mode is joint damage and subsequent yield loss during aqueous jet impingement. The move towards semiconductor grade ultralow residue no-clean fluxes and away from cleaning processes is therefore inevitable for both flip-chip and MEMS applications to meet industry roadmap challenges. The low residue also optimizes underfill adhesion and decreases possible outgassing during underfill cure. This paper discusses the variety of new and emerging failure modes for new packing processes using thinned die with copper-pillar/microbumps. The testing of assembly materials for this purpose will also be discussed.