Flash Operations Research Articles

CONTROLLER DESIGN FOR MULTICHANNEL NAND FLASH MEMORY FOR HIGHER EFFICIENCY IN SSD’S

Flash based storage system is presently very attractive in the market than the previous Magnetic disk drives. Flash memory is basically Non-Volatile memory; it means it can electrically erasable and programmable. The Flash memory has less power consumption and less latency compare to previous magnetic disk drives, this makes flash more attractive and popular. Flash memory basically comprises of three basic operations, they are Read, Write (program), and Erase. The Flash memory will be written in pages and will be erased in blocks. Functions of the multi-channel parallel controller are validated according to a wide spread of workloads. The proposed Flash controller develops its own method for the reorganization and mapping of invalid blocks in a Flash chip. This paper explains about new flash controller design and control signals for flash operations and also exploits the parallelism by using multiple channels or multiple controllers for single flash memory in order to reduce the further latency in read, write and erase operation.

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.

NAND Flash Memory Organization and Operations

NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base. Since cells in a flash chip will fail after a limited number of writes, limited write endurance is a key characteristic of flash memory. There are many noise causes such as read or program disturbs, retention process, charge leakage, trapping generation, etc. Preferably, all errors in the storage would be adjusted by the ECC algorithm. The conclusion of all mentioned parasitic factors creates a set of external and internal influences which affects variable behaviour of memory in time. To prepare a review of all the important factors that affect the reliability and life-cycle endurance of NAND flash memories and was our main motivation for this paper.

컬럼-지향 데이터베이스를 위한 컬럼-인지 트랜잭션 관리 기법

ABSTRACT The column-oriented database storage is a very advanced model f or large-volume data analysis systems because of its superior I/O performance. Traditional data storages exploit row-oriented storage where the attributes of a record are placed contiguously in hard disk for fast write operations. However, for search-mostly datawarehouse systems, column-oriented storage has become a mo re proper model because of its superior read performance. Recently , solid state drive using MLC flash memory is largely recognized as the preferred storage media for high-speed data analysis system s. The features of non-volatility, low power consumption, and f ast access time for read operations are sufficient grounds to suppo rt flash memory as major storage components of modern database servers. However, we need to improve traditional transaction management scheme due to the relatively slow characteristics of column compression and flash operation as compared to RAM memory. In this research, we propose a new scheme called Column-aware Multi-Version Locking (CaMVL) scheme for efficient transaction processing. CaMVL improves transaction performance by using compression lock and multi version reads f or efficiently handling slow flash write/erase operation in lock management process. We also propose a simulation model to show the performance of CaMVL. Based on the results of the performance evaluation, we conclude that CaMVL scheme outperfor ms the traditional scheme.

The Key Technology of Designing the Universal Programmer for Freescale HCS12 Serial MCUs

For implementing on-line programming of Freescale HCS12 series MCU, designing a common downloading programmer which functions include chip selection, erase and write operations. Designing a database where Freescale HCS12 MCU Flash difference parameter values ​​placed, so achieving HCS12 MCU family online programming versatility. Erase and write machine codes are provided in the RAM area of Flash memory, these codes will be run at high voltage, these codes are relocated from Flash to RAM area for improving flash operation stability during the high voltage. According to BDM communication theory, we have developed a separate BDM serial communication program, the target device only receives the user code from the programmer, programmer does not need send opcode and the address information, not waiting for a command, so, increasing the erase and write speed. the programmer has the versatility and easily using.

A visual approach to interpreting NAND flash memory

The research described in this paper proposes methods for visually interpreting the content of raw NAND flash memory images into higher level visual artefacts of assistance in reverse engineering and interpreting flash storage formats. A novel method of reverse engineering the structure and layout of individual memory locations within NAND flash images, based on injecting a known signal into a test NAND environment is also proposed. Omissions in the current theory of operation of flash, in particular the role of flash memory controllers in transforming the raw NAND are identified, clarifying the cause of variations seen between images taken using pseudo physical and raw physical techniques. The effectiveness of the approach is validated against raw NAND images from YAFFS2 based Android phones, taken via JTAG and chip-off methods.

Flashmon V2

This paper presents Flashmon version 2, a tool for monitoring embedded Linux NAND flash memory I/O requests. It is designed for embedded boards based devices containing raw flash chips. Flashmon is a kernel module and stands for "flash monitor". It traces flash I/O by placing kernel probes at the NAND driver level. It allows tracing at runtime the 3 main flash operations: page reads/writes and block erasures. Flashmon is (1) generic as it was successfully tested on the three most widely used flash file systems that are JFFS2, UBIFS and YAFFS, and several NAND chip models. Moreover, it is (2) non intrusive, (3) has a controllable memory footprint, and (4) exhibits a low overhead (< 6%) on the traced system. Finally, it is (5) simple to integrate and used as a standalone module or as a built-in function/module in existing kernel sources. Monitoring flash memory operations allows a better understanding of existing flash management systems by studying and analyzing their behavior. Moreover it is useful in development phase for prototyping and validating new solutions.

Flexible Design and Operation of Multi-Stage Flash (MSF) Desalination Process Subject to Variable Fouling and Variable Freshwater Demand

This work describes how the design and operation parameters of the Multi-Stage Flash (MSF) desalination process are optimised when the process is subject to variation in seawater temperature, fouling and freshwater demand throughout the day. A simple polynomial based dynamic seawater temperature and variable freshwater demand correlations are developed based on actual data which are incorporated in the MSF mathematical model using gPROMS models builder 3.0.3. In addition, a fouling model based on stage temperature is considered. The fouling and the effect of noncondensable gases are incorporated into the calculation of overall heat transfer co-efficient for condensers. Finally, an optimisation problem is developed where the total daily operating cost of the MSF process is minimised by optimising the design (no of stages) and the operating (seawater rejected flowrate and brine recycle flowrate) parameters.

Ferroelectric-Assisted Dual-Switching Speed DRAM–Flash Hybrid Memory

This paper presents a novel one-transistor low-voltage DRAM-Flash hybrid memory. The proposed device integrates ferroelectric thin film and nonvolatile charge injection, and demonstrates two modes of operations: 1) a fast (10-100 ns) DRAM mode with ~ 103 s of retention, associated with ferroelectric switching, and 2) a slower (0.1-1 ms) Flash mode with long retention time, from charge tunneling into the floating nodes. The time evolution of the electric field in the ferroelectric and the tunnel oxide is shown to naturally establish the two-step mechanism during the program operation. The complementary characteristics of ferroelectric switching and gate-charge injection enable low-voltage program/erase (±8 V), reasonable memory window (0.8 V), and long retention time. Devices were fabricated with the lead zirconatetitanate thin film as the ferroelectric layer and Au nanocrystals for gate-injected electron storage. Pulsed programming measurements were also performed to distinguish the memory window obtained from the two mechanisms in DRAM and Flash operations.

μ*-Tree: An Ordered Index Structure for NAND Flash Memory with Adaptive Page Layout Scheme

As NAND flash memory is gaining popularity as a storage medium for mobile embedded devices, many flash-aware file systems, flash-aware DBMSes, and flash translation layers (FTLs) require an flash-efficient index structure. This paper proposes a novel index structure called μ*-Tree which natively works on NAND flash memory, aiming at improving performance over B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree. μ*-Tree stores all the nodes along the path from the root to the leaf into a single flash memory page in order to minimize the number of flash write operation when a node is updated. Furthermore, μ*-Tree has an adaptive page layout scheme which dynamically adjusts the page layout according to the workload characteristics on-the-fly. μ*-Tree also allows flash pages with different page layouts to coexist in the same tree. Our evaluation results with real workload traces show that μ*-Tree outperforms B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree by up to 55 percent in terms of the time needed for flash operations. With a small in-memory cache of 32 KB, μ*-Tree improves the overall performance by up to five times compared to B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree with the same cache size.

Safety Evaluation of Discontinuing Late Nighttime Flash Operations at Signalized Intersections

This study examined the safety impacts of converting late nighttime flash operation to normal phasing operation at signalized intersections by using the empirical Bayes, the univariate full Bayes, and multivariate full Bayes before-and-after methods. Data were obtained from the North Carolina Department of Transportation for 61 treatment sites and 395 reference intersections that remained on late nighttime flash operation from 2000 to 2007. The results from the empirical Bayes method are almost identical to those of the univariate full Bayes. The full Bayes method offered more flexibility in selecting the functional form of expected crashes at similar sites (similar to the safety performance function in the empirical Bayes) and in addressing uncertainty in the data. Compared with the univariate full Bayes, the multivariate full Bayes with the multivariate Poisson lognormal (MVPLN) model provided better results based on much lower deviance information criterion values. The MVPLN model was favored and the recommended crash reduction factors are 48% (±6%), 53% (±8%), and 57% (±7%) for nighttime total, injury and fatal, and frontal impact crashes, respectively.

An Abstract Fault Model for NAND Flash Memory

We present an abstract fault model for NAND flash memory that describes precisely the effects of various faults during a flash operation. The abstract model is intended to be used to reason about fault-related correctness of key modules of flash memory management software such as a flash translation layer (FTL). We also introduce the concept of “SAO-compliance” to raise awareness about fault-related vulnerabilities of current flash memory management software and to promote much needed research to fix them.

A High Temp standalone 4MByte Flash memory with SPI Interface for 210C applications

This paper covers the internal architecture, testability &amp; performance characterization of Texas Instruments ™ High-Temp 210C 4MByte standalone Flash storage device. It will be available in a 14-pin ceramic dual Flat pack package as well as a Known Good Die (KGD) option. The device is manufactured in TI's 180nm 1.8V flash process with 3.3V IOs. The design implements 8 banks of flash organized into 2M × 16 bits surrounded by a SPI controller. The SPI controller interfaces asynchronously with an internal flash controller. The flash controller is clocked by FCLK, and controls the flash charge pump to access &amp; operate the flash to program, read, erase, validate etc. The SPI controller is responsible for translating and executing the high level SPI protocol commands to the internal flash controller &amp; its registers. A simple and flexible protocol was developed to access the flash array via the SPI supporting various commands and configuration capabilities. Testability of critical parameters for reliable 210C flash operation is ensured with the implementation of an internal test port accessible through a parallel interface (for TI Internal use only). The test port, and a SPI initiated BIST controller are used to provide full &amp; comprehensive characterization of the flash bit cell array, as well as the flash-pump across temperature &amp; frequencies. The form factor, size, and pin out of this flash device is primarily focused on data logging for narrow &amp; space limited extreme harsh environments such as the down-hole drilling industry.

Meeting Variable Freshwater Demand by Flexible Design and Operation of the Multistage Flash Desalination Process

In this work, the design and operation of multistage flash (MSF) desalination processes are optimized and controlled in order to meet variable demands of freshwater with changing seawater temperatu...

Vapor Compress Flash: Synthesis and Progress on Seawater Desalination Methods

Among the modern seawater desalination methods, this article analyzes and induces the question of the second vapor condensing latent heat loss of the open heat process in multi-stage flash. Then this article synthesizes its merits and proposes for the first time the newest and the best and integrated vapor compress flash seawater desalination method, in witch a flash with the best product water quality is driven by a vapor compress with the highest heat-power efficiency, with technical superiorities such as the lowest investment cost and independent flash operation and modularization combination production and so on.

Ozone (O3): An Out-of-Order Flash Memory Controller Architecture

Ozone (O3) is a flash memory controller that increases the performance of a flash storage system by executing multiple flash operations out of order. In the O3 flash controller, data dependencies are the only ordering constraints on the execution of multiple flash operations. This allows O3 to exploit the multichip parallelism inherent in flash memory much more effectively than interleaving. The O3 controller also provides a prioritized handling of flash operations, equipping flash management software, such as the FTL (flash translation layer), with control knobs for managing flash operations of different time criticalities. Running a range of workloads on an FPGA implementation showed that the O3 flash controller achieves 3 to 100 percent more throughput than interleaving, with 46 to 88 percent lower response times.

고속 임베디드 저장 시스템을 위한 복제전환 기법

The flash memory has been remarked as the next generation media of portable and desktop computers` storage devices. Their features include non-volatility, low power consumption, and fast access time for read operations, which are sufficient to present flash memories as major data storage components for desktop and servers. The purpose of our study is to upgrade a traditional mirroring scheme based on SSD storages due to the relatively slow or freezing characteristics of write operations, as compared to fast read operations. For this work, we propose a new storage management scheme called Memory Mirror-Switching based on traditional mirroring scheme. Our Mirror-Switching scheme improves flash operation performance by switching write-workloads from flash memory to RAM and delaying write operations to avoid freezing. Our test results show that our scheme significantly reduces the write operation delay and storage freezing.

An intermediate heat exchanging–depressurizing loop for nuclear hydrogen production

Sulfur–iodine (SI) cycle should overcome many engineering challenges to commercialize and prove its feasibilities to compete other thermo-chemical cycles. Some critical issues such as structural material, harsh operating condition and high capital costs were considered obstacles to be actualized. Operating SI cycle at low-pressure is one of the solutions to actualize the cycle. The flash operation with over-azeotropic HI at low pressure does not require temperature and pressure as high as those in the existing methods as well as heating for separation. The operation in low pressure reduces corrosion problems and enables us to use flexible selection of structural material. We devised an intermediate heat exchanging–depressurizing loop to eliminate high operating pressure in the hydrogen side as well as a large pressure difference between the reactor side and the hydrogen side. Molten salts are adequate candidates as working fluids under the high-temperature condition with homogeneous phase during pressure changing process. Using molten salts, 2.20–4.65 MW of pumping work is required to change the pressure from 1 bar to 7 MPa. We selected BeF 2-containing salts as the possible candidates based on preliminary economic and thermal hydraulic consideration.

Performance characteristics of a once-through multi-stage flash distillation process

Many process variables are involved in the design and operation of a multi-stage flash (MSF) distillation process. An estimation of the effect of these parameters on the plant performance is important to improve the optimum operating conditions. Both analytical solutions and experimental/ field analysis are required to identify the most influential parameters that affect the performance and set proper plans for performance optimization. The accurate estimate of the variables related to the brine heater, selecting proper number of stages and the stage-to-stage temperature drop are of crucial importance. In addition, the thermal properties dependent on the operating conditions may affect the accuracy of numerical results. Moreover, the salinity of the feed seawater has a significant effect on the plant characteristics. In this study, the effect of various operating conditions on the performance ratio, brine temperature and salinity as it leaves the last flash stage are investigated in a once-through system. The up-to-date reliable correlations for calculating brine properties that vary with both temperature and salinity are used. The numerical results obtained by the present investigation are compared with the published data on similar plants. A sensitivity analysis to identify the key parameters that significantly influence the desalination plant performance is carried out in an attempt to contribute a better understanding on modeling and optimum operation of MSF desalination processes.

A large-scale cryoelectronic system for biological sample banking

We describe a polymorphic electronic infrastructure for managing biological samples stored over liquid nitrogen. As part of this system we have developed new cryocontainers and carrier plates attached to Flash memory chips to have a redundant and portable set of data at each sample. Our experimental investigations show that basic Flash operation and endurance is adequate for the application down to liquid nitrogen temperatures. This identification technology can provide the best sample identification, documentation and tracking that brings added value to each sample. The first application of the system is in a worldwide collaborative research towards the production of an AIDS vaccine. The functionality and versatility of the system can lead to an essential optimization of sample and data exchange for global clinical studies.