Abstract

NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base. Since cells in a flash chip will fail after a limited number of writes, limited write endurance is a key characteristic of flash memory. There are many noise causes such as read or program disturbs, retention process, charge leakage, trapping generation, etc. Preferably, all errors in the storage would be adjusted by the ECC algorithm. The conclusion of all mentioned parasitic factors creates a set of external and internal influences which affects variable behaviour of memory in time. To prepare a review of all the important factors that affect the reliability and life-cycle endurance of NAND flash memories and was our main motivation for this paper.

Highlights

  • Flash memory has been an important driving force due to the increasing popularity of mobile devices with large storage requirements

  • NAND flash memory has become very popular for usage in various applications where a large amount of data has to be stored

  • This article discusses important aspects related to the NAND Flash memory, storage reliability and the actual bit error rate

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Summary

Introduction

Flash memory has been an important driving force due to the increasing popularity of mobile devices with large storage requirements. The basic unit of operation for a NAND Flash device is one page of data with some commands influencing the whole block. This dictates the need to have the size of data I/O register equal to the page size. NAND Flash memory reads and writes in high-speed, sequential mode, handling data in pages Differences such as cache programming, random programming and two plane programming are enabled only by some NAND Flash devices. Since NAND flash does not offer a random-access external address bus the required data are read on a block-wise basis ( termed as page access), where each block keeps hundreds to thousands of bits, similar to a kind of sequential data access. The bit error rate or bit error ratio (BER) is the number of bits that have errors divided by the total quantity of

32 Gb MLC 8 Gb SLC
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