Abstract
Flash based storage system is presently very attractive in the market than the previous Magnetic disk drives. Flash memory is basically Non-Volatile memory; it means it can electrically erasable and programmable. The Flash memory has less power consumption and less latency compare to previous magnetic disk drives, this makes flash more attractive and popular. Flash memory basically comprises of three basic operations, they are Read, Write (program), and Erase. The Flash memory will be written in pages and will be erased in blocks. Functions of the multi-channel parallel controller are validated according to a wide spread of workloads. The proposed Flash controller develops its own method for the reorganization and mapping of invalid blocks in a Flash chip. This paper explains about new flash controller design and control signals for flash operations and also exploits the parallelism by using multiple channels or multiple controllers for single flash memory in order to reduce the further latency in read, write and erase operation.
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