Flash Memory Storage Research Articles

Design and implementation of efficient bootloader for endurance enhancement in flash memory storage systems

We propose a new bootloader design with dynamic boot addressing to increase the endurance of microcontroller flash memories and to use flash memory efficiently.Although the final industrial products are not updated much, regular programming during the development and testing phase inefficiently reduces the endurance of flash memory. Especially after the pandemic, the problems experienced in the production/supply processes of products using semiconductor technology and the highly extended deadlines have inspired our work to extend the life of the products used in the development and testing phase.Within the scope of the study, a bootloader design and implementation related to increasing the durability of flash memory, which affects the lifetime of microcontrollers, are explained.When a new application installation request comes, it is aimed to provide the following without the need for any additional hardware; It is to ensure that the data to be written to the flash memory is shared homogeneously between sectors, to prevent unnecessary memory deletion, to shorten the time spent on installing applications, to increase memory endurance and to predict possible memory endurance problems.

Optimized design of an extreme low power datalogger for photovoltaic panels

<span lang="EN-US">The paper focuses on the design and implementation of a low cost and compact data logger prototype using an extreme low power (XLP) and low pin count programmable interface controllers (PIC) microcontroller using its own flash memory for the periodic data acquisition storage, while many other works focus in the Arduino Eco-system. It is planned to pick four important analog measures from the photovoltaic system, and store them directly as 10-bit numerical counts, this yields to faster data acquisition and storage (no time consuming for mathematical computation to convert each numerical count of raw data to meaningful real-world data). Avoiding the use of any kind of display and keypad, and keeping the ratio run time over sleep time as low as possible, has a maximum impact on lowering the power consumption. This prototype can be serially linked to a personal computer (PC) to view the acquisition of measurements in real time, and to retrieve all collected data through a terminal application. The experimental results are stored in comma-separated values (CSV) files to ease post data analysis with any spread sheet software, for statistical calculations and graphs drawing, in order for instance, to find the faults of the photovoltaic system and optimize its management and its performance.</span>

Effect of Mask Geometry Variation on Plasma Etching Profiles

It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, "there's plenty of room at the top". The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF6/O2 is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF6/O2 plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules.

A Supervised-Learning-Based Garbage Collection in Solid-State Drives (SSDs)

Garbage collection (GC) plays an important role in solid-state drives (SSDs) that adopt NAND flash memory for storage. When SSDs run out of free space, SSDs will perform the garbage collection until free space is enough. Therefore, GC can be considered as overhead because it requires additional copy/erase overhead and decreases the overall I/O performance. In this article, we will investigate a supervised-learning-based garbage collection to properly trigger the garbage collection at the right time and also improve the response time of I/O requests. According to the experimental results, we can demonstrate that the proposed method can achieve the objective.

FTRM: A Cache-Based Fault Tolerant Recovery Mechanism for Multi-Channel Flash Devices

Flash memory prevalence has reached greater extents with its performance and compactness capabilities. This enables it to be easily adopted as storage media in various portable devices which includes smart watches, cell-phones, drones, and in-vehicle infotainment systems to mention but a few. To support large flash storage in such portable devices, existing flash translation layers (FTLs) employ a cache mapping table (CMT), which contains a small portion of logical page number to physical page number (LPN-PPN) mappings. For robustness, it is of importance to consider the CMT reconstruction mechanisms during system recovery. Currently, existing approaches cannot overcome the performance penalty after experiencing unexpected power failure. This is due to the disregard of the delay caused by inconsistencies between the cached page-mapping entries in RAM and their corresponding mapping pages in flash storage. Furthermore, how to select proper pages for reconstructing the CMT when rebooting a device needs to be revisited. In this study we address these problems and propose a fault tolerant power-failure recovery mechanism (FTRM) for flash memory storage systems. Our empirical study shows that FTRM is an efficient recovery and robust protocol.

A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices

As flash memory technology has been scaled down to 1x nm and more bits can be stored in a cell, the storage density of flash memory has been significantly improved. However, these technical trends also severely hurt the programming speed and endurance of flash memory. The internal data retention time is the duration for which a flash cell can correctly hold data. By relaxing internal data retention time, both the page programming speed and the block endurance could be improved. However, the retention time of flash memory typically requires to last for several years according to the industrial standard. Thus a refreshment scheme is required to deal with the decreasing of retention time. In this article, we propose multi-level retention-time queues with a management scheme to meet the retention-time requirement for a reliable storage system. Observing that many data are overwritten in hours or days in real workloads, multiple retention-time queues could effectively separate data with different update frequencies. There are three challenge issues for a proper design: (1) Since access pattern might change from time to time, a technical issue is how to promote/demote data so that data could be maintained in the proper retention-time queue to minimize the refreshment overhead. (2) Another technical issue is how to refresh each retention-time queue in time to guarantee data integrity. (3) Since blocks resided in different retention-time queue would suffer from different level of wearing, the third technical issue is how to estimate wearing status of flash-memory blocks in an effective and efficient manner to achieve wear leveling. In our scheme, data allocator, multi-level refresh module, garbage collector, and wear leveler are introduced to deal with these technical issues. Based on our experimental results, not only endurance and performance but also energy consumption of the flash-memory storage system could be significantly improved by our scheme.

A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices

The storage capacity of the NAND flash memory has increased rapidly, and accordingly, the error rate for data writing and reading to the flash memory cell has also escalated. Error-correcting code (ECC) modules, such as low-density parity-check (LDPC), have been applied to flash controllers for error recovery. However, since the error rate increases rapidly, compared to the aging factor and program/erase (P/E) cycle, fixed ECCs and parities are inappropriate methods for resolving this proliferating error, according to the P/E cycle. Therefore, the design of a dynamic ECC scheme and a proper ECC parity management system to increase the lifespan of flash memory storage devices remains in great demand. Herein, an LDPC encoding and decoding scheme is designed to obtain a step-by-step code rate according to the P/E cycle by applying a stepwise rate-compatible LDPC. In addition, an ECC parity management scheme for the increasingly excessive stage-wise ECC is proposed to reduce management and read/write operational overheads. The ECC management scheme also includes the ECC cache system. The proposed LDPC, as well as its management system, will improve the recovery ability of the NAND flash storage device according to the P/E cycle, while it can reduce system read and write overheads due to additional parity data growth.

DCR: Deterministic Crash Recovery for NAND Flash Storage Systems

NAND flash memory has been widely adopted as the storage medium. As power failure may occur at any time and result in data loss, crash recovery becomes vitally important in NAND flash memory storage systems. Since flash translation layers (FTLs) are used to manage flash memory, the crash recovery problem in NAND flash is how to efficiently and effectively recover FTL metadata with consistency after system crash. In this paper, we present deterministic crash recovery (DCR) that adopts a deterministic approach for crash recovery in NAND flash storage systems. The basic idea is to exploit the determinism of FTLs and reproduce events that happened between the last checkpoint and the crash point during crash recovery. Different from existing approaches that need to scan the whole flash memory chip, DCR can recover the system more efficiently by only checking a limited number of blocks based on deterministic FTL operations. We have implemented DCR in an FTL and compared it with the representative version-based and power loss recovery schemes based on an ARM-based embedded system. Experimental results show that DCR can greatly reduce the recovery time and guarantee the consistency of FTL metadata after recovery.

Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages

During the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size. Wear leveling is a general solution used to alleviate this issue; it enables cells to wear down evenly but it cannot actually mitigate the wearing of the cells. Accordingly, techniques are required to minimize the actual cell degradation. This paper proposes <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">endurance-enhancing lower state encoding</i> . The key insight leveraged by the proposed technique is the data pattern-related characteristic of MLC and TLC NAND flash memories, in which the lower the state of the cells, the lower the occurrence of wear out. Thus, our proposed scheme encodes input data to make the cell state as low as possible in consideration of interpage relation. As a result, the wear out of the memory cells can be minimized and their lifetime is improved by 62.7% in a file type and 43.0% in MySQL. Experimental results indicate that our scheme shows better lifetime improvement than other schemes in most cases.

MEM-FLASH non-volatile memory device for high-temperature multibit data storage

We demonstrate microelectromechanical system-based flash memory (MEM-FLASH) for multinary bit storage. The MEMS switch integrated with the transistor provides the precise control of the charges on the floating gate. This maneuvering of the charges to 8 different levels provides 3-bit operation even at an elevated temperature of ∼300 °C. The key challenge in the realization of such a memory is the know-how the amount of charge to be transferred to the floating gate to alter the bit state. The charge estimation on the floating gate cannot be performed by direct probing of the device, as this will disturb the original charge values of the floating gate and thus the threshold value. Ergo, an indirect read approach is developed. Furthermore, the cantilever switch is fabricated and tested in a vacuum environment for experimental validation of the approach. The percentage variation from the theoretical to experimental approach is in the adoptable limit of 2%.

Validation of modified radio-frequency identification tag firmware, using an equine population case study.

BackgroundContact networks can be used to assess disease spread potential within a population. However, the data required to generate the networks can be challenging to collect. One method of collecting this type of data is by using radio-frequency identification (RFID) tags. The OpenBeacon RFID system generally consists of tags and readers. Communicating tags should be within 10m of the readers, which are powered by an external power source. The readers are challenging to implement in agricultural settings due to the lack of a power source and the large area needed to be covered.MethodsOpenBeacon firmware was modified to use the tag’s onboard flash memory for data storage. The tags were deployed within an equine facility for a 7-day period. Tags were attached to the horses’ halters, worn by facility staff, and placed in strategic locations around the facility to monitor which participants had contact with the specified locations during the study period. When the tags came within 2m of each other, they recorded the contact event participant IDs, and start and end times. At the end of the study period, the data were downloaded to a computer and analyzed using network analysis methods.ResultsThe resulting networks were plausible given the facility schedule as described in a survey completed by the facility manager. Furthermore, changes in the daily facility operations as described in the survey were reflected in the tag-collected data. In terms of the battery life, 88% of batteries maintained a charge for at least 6 days. Lastly, no consistent trends were evident in the horses’ centrality metrics.DiscussionThis study demonstrates the utility of RFID tags for the collection of equine contact data. Future work should include the collection of contact data from multiple equine facilities to better characterize equine disease spread potential in Ontario.

Optimizing Retention-Aware Caching in Vehicular Networks

Caching is an effective way to address the challenges due to explosive data traffic growth and massive device connectivity in fifth-generation (5G) networks. Currently, few works on caching pay attention to the impact of the time duration for which content is stored, called retention time, on caching optimization. The research on retention time is motivated by two practical issues, i.e., flash memory damage and storage rental cost in cloud networks, together giving rise to the storage cost. How to optimize caching contents taking the storage cost into consideration is a challenging problem, especially for the scenarios with cache-enabled mobile nodes. In this paper, a retention-aware caching problem (RACP) in vehicular networks is formulated, considering the impact of the storage cost. The problem’s complexity analysis is provided. For symmetric cases, an optimal dynamic programming (DP) algorithm with polynomial time complexity is derived. For general cases, a low complexity and effective retention aware multi-helper caching algorithm (RAMA) is proposed. Numerical results are used to verify the effectiveness of the algorithms.

SlimFS: A Thin and Unobtrusive File System for Embedded Systems and Consumer Products

It is common place for embedded systems and consumer products to contain flash memory for nonvolatile storage. While there are many applications that require the data stored in the flash memory to be in a given structure enabling the data to be externally accessed, there are also many embedded consumer applications where the content of the flash memory is only accessed locally. In this case, the local application can benefit from having a minimized bespoke file system optimized for the application, resulting in lower power and faster access speed than using public file systems. This paper analyzes the overhead in using the commonly used file allocation table file system, and proposes a significantly faster, smaller footprint, and hence lower power file system, termed SlimFS. The work has clear applications to low power embedded consumer applications, specifically battery driven wearable devices for healthcare and “green” electronic systems.

DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems

NAND flash has been widely adopted in storage systems due to its better read and write performance and lower power consumption over traditional mechanical hard drives. To meet the increasing performance demand of modern applications, recent studies speed up flash accesses by exploiting access latency variations at the device level. Unfortunately, existing flash access schedulers are still oblivious to such variations, leading to suboptimal I/O performance improvements. In this paper, we propose DLV, a novel flash access scheduler for exploring scheduling opportunities due to device level access latency variations. DLV improves flash access speeds based on process variations and data retention time difference across flash blocks. More importantly, DLV integrates access speed optimization with access scheduling such that the average access response time can be effectively reduced on flash memory storage systems. Our experimental results show that DLV achieves an average of 41.5% performance improvement over the state-of-the-art.

Efficient low‐complexity two‐dimensional equalisation technique for multi‐level cell flash memory storage systems

NAND flash memories, due to their several advantageous characteristics, have recently dominated the data storage industry and its global market. Currently, multi-level cell memories, in which each cell can store more than one bit of data resulting in higher data storage capacities, have gained a considerable amount of research interest. However, this comes at the cost of several limitations and increased performance degradation. Various studies have shown that among several error sources in multi-level cell memories, inter-cell interference is the most significant one. Therefore, to mitigate the devastating effect of the interference, simple, feasible, and yet efficient equalisation techniques become essential for achieving desired data reliability. In this study, first, a thorough analysis on deriving the distribution of the interference-free and interference-affected data is carried out. Then, novel low-complexity equalisation methods are proposed, and their beneficial complexity-performance trade-offs compared with the existing techniques are illustrated. Finally, simulation results are presented to show that the proposed algorithms considerably improve the error performance, while maintaining the low-complexity constraints.

Three advances make magnetic tape more than a memory [News

In the age of flash memory and DNAbased data storage, magnetic tape sounds like an anachronism. But the workhorse storage technology is racing along. Scientists at IBM Research say they can now store 201 gigabits per square inch on a special sputtered tape made by Sony Storage Media Solutions. The palm-size cartridge, into which IBM scientists squeezed a kilometer-long ribbon of tape, could hold 330 terabytes of data, or roughly 330 million books' worth. By comparison, the largest solid-state drive, made by Seagate, is twice as big and can store 60 TB, while the largest hard disk can store only 12 TB. IBM's best commercial tape cartridge, which began shipping this year, holds 15 TB.

A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems

NAND flash memory is the major storage media for both mobile storage cards and enterprise Solid-State Drives (SSDs). Log-block-based Flash Translation Layer (FTL) schemes have been widely used to manage NAND flash memory storage systems in industry. In log-block-based FTLs, a few physical blocks called log blocks are used to hold all page updates from a large amount of data blocks. Frequent page updates in log blocks introduce big overhead so log blocks become the system bottleneck. To address this problem, this paper presents BLog , a block-level log-block management scheme for MLC NAND flash memory storage system. In BLog, with block-level management, the update pages of a data block can be collected together and put into the same log block as much as possible; therefore, we can effectively reduce the associativities of log blocks so as to reduce the garbage collection overhead. We also propose a novel partial merge operation strategy called reduced-order merge by which we can effectively postpone the garbage collection of log blocks so as to maximally utilize valid pages and reduce unnecessary erase operations in log blocks. Based on BLog, we design an FTL called BLogFTL for Multi-Level Cell (MLC) NAND flash. We conduct a set of experiments on a real hardware platform. Both representative FTL schemes and the proposed BLogFTL have been implemented in the hardware evaluation board. The experimental results show that our scheme can effectively reduce the garbage collection operations and reduce the system response time compared to the previous log-block-based FTLs for MLC NAND flash.

Implicit Programming: A Fast Programming Strategy for nand Flash Memory Storage Systems Adopting Redundancy Methods

The aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell of NAND flash memory inevitably degrade the reliability of NAND flash. Redundancy methods have been widely adopted to enhance the reliability of the system data in NAND flash memory. However, the redundancy process will induce extra program operations which will sharply degrade the I/O performance of the system. This letter presents implicit programming strategy, a fast redundancy strategy for NAND flash memory storage systems adopting redundancy methods. Our technique for the first time exploits the property of the copyback operation and combines the normal program operation and copyback program operation to reduce the I/O performance overhead induced by the redundancy process. We have implemented implicit programming on a real hardware platform. The experimental results shoChang-DAC09w that by combining with implicit programming, one redundancy scheme (Meta-Cure) can reduce up to 27.24% of the I/O performance overhead.

Virtual duplication and mapping prefetching for emerging storage primitives in NAND flash memory storage systems

NAND flash memory has become the mainstream storage medium for both enterprise high performance computers and embedded systems. However, over the past several decades, the storage primitives that access secondary storage have remained unchanged, forcing NAND flash memory to serve merely as a block device like hard disk drive. Recently, several emerging storage primitives have been presented to explore the potential value of non-volatile memory devices. Although these primitives can significantly boost the access performance by providing virtual to logical address mappings, they still suffer from large RAM footprint to maintain the address mapping table and require further support for update operations.This paper presents ESP to optimize E merging S torage P rimitives with virtualization for flash memory storage systems. We propose two optimization strategies, virtual duplication and mapping prefetching to solve the critical issues in existing emerging storage primitives. The objective is to reduce unnecessary flash memory accesses and keep RAM footprint of address mapping table well under control. We have evaluated ESP on an embedded development platform. Experimental results show that ESP can significantly improve the write/read performance and reduce over 30% of garbage collection operations.

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems

During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of nonvolatile flash in the system’s memory hierarchy. The increasing capacity of NAND flash memory introduces a large RAM footprint to store the logical to physical address mapping. The demand-based approach can effectively reduce and well control the RAM footprint. However, extra address translation overhead is also introduced which may degrade the system performance. In this article, we present CDFTL, an adaptive Caching mechanism for Demand-based Flash Translation Layer, for NAND flash memory storage systems. CDFTL adopts both the fine-grained entry-based caching mechanism to exploit temporal locality and the coarse-grained translation-page-based caching mechanism to exploit spatial locality of workloads. By selectively caching the on-demand address mappings and adaptively changing the space configurations of two granularities, CDFTL can effectively utilize the RAM space and improve the cache hit ratio. We evaluate CDFTL under a real hardware embedded platform using a variety of I/O traces. Experimental results show that our technique can achieve an 11.13% reduction in average system response time and a 35.21% reduction in translation block erase counts compared with the previous work.