Flash Memory Array Research Articles

Demonstration of In-Memory Biosignal Analysis: Novel High-Density and Low-Power 3D Flash Memory Array for Arrhythmia Detection.

Smart healthcare systems integrated with advanced deep neural networks enable real-time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND-type flash memory array with a rounded double channel for computing-in-memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low-power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life-threatening arrhythmias. Incorporated with a simplified spike-timing-dependent plasticity learning rule, the CIM architecture is suitable for robust, area- and energy-efficient in-memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm.

Flash-Based Computing-in-Memory Architecture to Implement High-Precision Sparse Coding.

To address the concerns with power consumption and processing efficiency in big-size data processing, sparse coding in computing-in-memory (CIM) architectures is gaining much more attention. Here, a novel Flash-based CIM architecture is proposed to implement large-scale sparse coding, wherein various matrix weight training algorithms are verified. Then, with further optimizations of mapping methods and initialization conditions, the variation-sensitive training (VST) algorithm is designed to enhance the processing efficiency and accuracy of the applications of image reconstructions. Based on the comprehensive characterizations observed when considering the impacts of array variations, the experiment demonstrated that the trained dictionary could successfully reconstruct the images in a 55 nm flash memory array based on the proposed architecture, irrespective of current variations. The results indicate the feasibility of using Flash-based CIM architectures to implement high-precision sparse coding in a wide range of applications.

DAC: A dynamic active and collaborative cache management scheme for solid state disks

NAND Flash memory-based SSDs have been widely used in modern storage systems to improve the performance and energy consumption. Existing caching management schemes rarely consider the utilization of parallel resources in flash memory array inside an SSD while these parallel resources cannot be fully exploited. The I/Os-access conflicts deteriorate the SSD performance and enlarge the response time under write-intensive workloads. Most cache replacement strategies give priority to clean data to improve the I/O-access conflicts, thereby boosting the SSD performance. However, clean data entirely depends on missed read-I/Os requests. Ideally, data replacement ought to evict clean data in the cache thanks to low replacement cost. As such, flash memory-based caching schemes give the highest priority to clean data. However, the proportion of replaced clean data is low in cache data. To solve this issue, we propose a dynamic active and collaborative cache management named DAC, in which the cache is composed of cold cache, hot cache, ghost cold cache, and ghost hot cache. DAC determines hot-cold changes of the I/O requests in workloads based on ghost cache size, thereby adjusting the real cache size to well serve I/O requests. The dynamic write-back window (DWW) mechanism dynamically adjusts the write-back window size in the cold cache. The write-back thresholds automatically update according to the changes in I/O patterns in workloads. When a flash chip is in the idle state, DAC produces clean data by proactively writing normal cold cache data back into flash memory, and the clean data is migrated into the active cold cache. DAC prioritizes replacing data in the active cold cache, aiming to avoid evicting data that are just read from flash memory. This method is adept at boosting the replacement rate of clean data, thereby optimizing SSD performance. We undertake extensive experiments in the latest NVMe SSD simulator to validate the DAC’s edge over the seven existing caching schemes including LRU, CFLRU, GCaR-CFLRU, LCR, ARC, AD-LRU, and MQsim. The results unveil that our DAC shortens the response time by up to 60.8% with an average optimization rate of 24.4%. When it comes to response-time cliff, the maximum improvement offered by DAC reaches approximately 68.71%; meanwhile, DAC delivers an average optimization rate of 26.9%. Besides, the number of erase count reduces by up to 93.3% with an average improvement rate of 17.04%.

Circuit-Level Memory Technologies and Applications based on 2D Materials.

Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

An epidermal electronic system for physiological information acquisition, processing, and storage with an integrated flash memory array.

Epidermal electronic systems that simultaneously provide physiological information acquisition, processing, and storage are in high demand for health care/clinical applications. However, these system-level demonstrations using flexible devices are still challenging because of obstacles in device performance, functional module construction, or integration scale. Here, on the basis of carbon nanotubes, we present an epidermal system that incorporates flexible sensors, sensor interface circuits, and an integrated flash memory array to collect physiological information from the human body surface; amplify weak biosignals by high-performance differential amplifiers (voltage gain of 27 decibels, common-mode rejection ratio of >43 decibels, and gain bandwidth product of >22 kilohertz); and store the processed information in the memory array with performance on par with industrial standards (retention time of 108 seconds, program/erase voltages of ±2 volts, and endurance of 106 cycles). The results shed light on the great application potential of epidermal electronic systems in personalized diagnostic and physiological monitoring.

Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2.

Machine learning and signal processing on the edge are poised to influence our everyday lives with devices that will learn and infer from data generated by smart sensors and other devices for the Internet of Things. The next leap toward ubiquitous electronics requires increased energy efficiency of processors for specialized data-driven applications. Here, we show how an in-memory processor fabricated using a two-dimensional materials platform can potentially outperform its silicon counterparts in both standard and nontraditional Von Neumann architectures for artificial neural networks. We have fabricated a flash memory array with a two-dimensional channel using wafer-scale MoS2. Simulations and experiments show that the device can be scaled down to sub-micrometer channel length without any significant impact on its memory performance and that in simulation a reasonable memory window still exists at sub-50 nm channel lengths. Each device conductance in our circuit can be tuned with a 4-bit precision by closed-loop programming. Using our physical circuit, we demonstrate seven-segment digit display classification with a 91.5% accuracy with training performed ex situ and transferred from a host. Further simulations project that at a system level, the large memory arrays can perform AlexNet classification with an upper limit of 50 000 TOpS/W, potentially outperforming neural network integrated circuits based on double-poly CMOS technology.

A Noise-Resilient Neuromorphic Digit Classifier Based on NOR Flash Memories with Pulse–Width Modulation Scheme

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment

A hardware-based neural network that enables on-chip training using a thin-film transistor-type AND flash memory array architecture is designed. The synaptic device constituting the array is characterized by a doped p-type body, a gate insulator stack composed of SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , and a partially curved poly-Si channel. The body reduces the circuit burden on the high voltage driver required for both the source and drain lines when changing the synaptic weights. The high- κ material included in the gate insulator stack helps to lower the operating voltage of the device. As the device scales down, the structural characteristics of the device have the potential to increase the efficiency of the memory operation and the immunity to the voltage drop effect that occurs in the bit-lines of the array. In an AND array architecture using fabricated synaptic devices, a pulse scheme for selective memory operation is proposed and verified experimentally. Due to the direct feedback alignment (DFA) algorithm, which does not need to have the same synaptic weight in the forward path and backward path, the AND array architecture can be utilized in designing an efficient on-chip training neural network. Pulse schemes suitable for the proposed AND array architecture are also devised to implement the DFA algorithm in neural networks. In a system-level simulation, a recognition accuracy of up to 97.01% is obtained in the MNIST pattern learning task based on the proposed pulse scheme and computing architecture.

Flash Memory Array for Efficient Implementation of Deep Neural Networks

The advancement of artificial intelligence applications is promoted by developing deep neural networks (DNNs) with increasing sizes and putting forward higher computing power requirements of the processing devices. However, due to the process scaling of complementary metal–oxide–semiconductor technology approaches to the end and the bottleneck of data transmission in the von‐Neumann architecture, traditional processing devices are increasingly challenging to meet the requirements of deeper and deeper neural networks. In‐memory computing based on nonvolatile memories has emerged as one of the most promising solutions to overcome the bottleneck of data transmission in the von‐Neumann architecture. Herein, systematic implementation of the novel flash memory array‐based in‐memory computing paradigm for DNNs from the device level to the architecture level is presented. The methodology to construct multiplication‐and‐accumulation units with different structures, hardware implementation schemes of various neural networks, and the discussion of reliability are included. The results show the hardware implementations of the flash memory array‐based in‐memory computing paradigm for DNN own excellent characteristics such as low‐cost, high computing flexibility, and high robustness. With these advantages, in‐memory computing paradigms based on flash memory arrays show significant benefits to achieve high scalability and DNNs’ energy efficiency.

Unsupervised Learning by Spike-Timing-Dependent Plasticity in a Mainstream NOR Flash Memory Array—Part I: Cell Operation

This article and its part II demonstrate the possibility to operate a mainstream NOR Flash memory array as an artificial synaptic array learning without external supervision according to the spike-timing-dependent plasticity (STDP) rule. As a first mandatory step to this aim, suitable array working conditions allowing not only selective cell programming but also selective cell erase are here identified, overcoming the block erase operation typical of any Flash memory technology. The proposed array working conditions exploit channel hot-electron injection and hot-hole injection at the drain side to achieve selective, bidirectional, and virtually analog tuning of cell threshold voltage, with no need for changes in the design of a common-ground double-polysilicon NOR array. In part II, the new working scheme will be shown to allow for a straightforward implementation of STDP and unsupervised learning in the array.

Unsupervised Learning by Spike-Timing- Dependent Plasticity in a Mainstream NOR Flash Memory Array—Part II: Array Learning

In this article, we show that, by exploiting the program and erase conditions identified in Part I of this article, operating a mainstream NOR Flash memory array as an artificial synaptic array learning in an unsupervised manner according to the spike-timing-dependent plasticity (STDP) rule can be easily achieved. To this aim, first, a word-line and a bitline voltage scheme allowing cells to change their memory state and, in turn, their synaptic weight to mimic the STDP learning rule is presented. Then, a simple spiking neural network making use of the NOR Flash array as a synaptic array is discussed along with its basic operating waveforms. Finally, the proof of concept for unsupervised learning in the array of a signal pattern provided at the network inputs is given.

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future.

Grayscale Image Recognition Using Spike-Rate-Based Online Learning and Threshold Adjustment of Neurons in a Thin-Film Transistor-Type NOR Flash Memory Array.

As a synaptic device, TFT-type NOR flash memory cell shows reasonable weight levels (50 levels for long-term potentiation (LTP) and 150 levels for long-term depression (LTD)) and large max/min ratio (═50) for synapse weight. Based on the measurement results of the synapse cell, supervised learning process is simulated using software MATLAB. A new pulse scheme is designed for mimicking spike-rate-dependent plasticity (SRDP) algorithm. Through learning and inferencing phase, our (784 × 100) network achieved 74.08% accuracy on the MNIST benchmark. A new method for adapting the threshold voltage of output neurons for firing is also proposed. This additional adjustment helps to eliminate the exclusive or dormant output neurons by setting the threshold voltage to an appropriate value proportional to the average weight of synapses connected to each neuron. As a result, accuracy increases to 82.54% in the (784 × 100) network and to 84.14% in the (784 × 200) network. Moreover, threshold adjustment helped the network to classify completely overlapped patterns in succession.

Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a Thin-Film Transistor-Type NOR Flash Memory Array.

We present a two-layer fully connected neuromorphic system based on a thin-film transistor (TFT)-type NOR flash memory array with multiple postsynaptic (POST) neurons. Unsupervised online learning by spike-timing-dependent plasticity (STDP) on the binary MNIST handwritten datasets is implemented, and its recognition result is determined by measuring firing rate of POST neurons. Using a proposed learning scheme, we investigate the impact of the number of POST neurons in terms of recognition rate. In this neuromorphic system, lateral inhibition function and homeostatic property are exploited for competitive learning of multiple POST neurons. The simulation results demonstrate unsupervised online learning of the full black-and-white MNIST handwritten digits by STDP, which indicates the performance of pattern recognition and classification without preprocessing of input patterns.

Hardware Security Primitive Exploiting Intrinsic Variability in Analog Behavior of 3-D NAND Flash Memory Array

The 3-D NAND flash memory has become an integral part of the cyber-physical systems to cope with the huge data explosion in this era of Internet of Things (IoT). Moreover, hardware security primitives such as physical unclonable function (PUF) have become indispensable in the functional circuits of these cyber-physical systems for protection against security vulnerabilities and adversary attacks. Therefore, in this paper, for the first time, we propose a PUF exploiting the intrinsic variability in the string current of the ubiquitous 3-D NAND flash memory owing to the process variations and the inherent material imperfections such as grain boundaries and the associated traps. With the aid of the Monte Carlo simulations utilizing a calibrated compact model for 3-D nand flash memory, we demonstrate that the proposed PUF exhibits excellent performance metrics such as uniformity (UF) (50%), diffuseness (DF) (50%), and uniqueness (UQ) (50.08%) and is resilient to the machine learning attacks. The ultradense 3-D NAND flash memory array also enables a significantly large set of challenge-response pairs (CRPs) for a strong PUF action.

Investigation of the temperature dependence of random telegraph noise fluctuations in nanoscale polysilicon-channel 3-D Flash cells

By gathering statistical data from floating-gate cells in a state-of-the-art 3-Dimensional (3-D) NAND Flash memory array, in this paper we explore the temperature dependence of random telegraph noise (RTN) fluctuations in nanoscale polysilicon-channel metal-oxide-semiconductor field-effect transistors. Experimental results highlight some major differences in the RTN temperature behavior with respect to monocrystalline silicon devices. In particular, not only the time constants but also the amplitude of RTN fluctuations appear to significantly change with temperature, with the latter displaying an average increase when temperature is reduced. The change of the fluctuation amplitude with temperature is correlated neither with the fluctuation time constants nor with their activation energy. Results are explained in terms of a more relevant role played by polysilicon grain boundaries when temperature is reduced, leading to a more percolative conduction in the transistor channel and to a stronger impact on the source-to-drain current of RTN traps placed close to the grain boundaries. These results should be carefully considered when attempting spectroscopic investigations based on the assumption, valid for monocrystalline devices, that only the time constants and not the amplitude of RTN fluctuations change with temperature.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory**Project supported by the National Natural Science Foundation of China (Grant No. 616340084), the Youth Innovation Promotion Association of CAS (Grant No. 2014101), the International Cooperation Project of CAS, and the Austrian-Chinese Cooperative R&D Projects (Grant No. 172511KYSB20150006).

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated 129Xe and 209Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 MeV/(mg/cm2). When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded, and only 0->1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer (LET). Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET 129Xe ions. The percolation path between the floating-gate (FG) and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

Lifespan Analysis for Redundant Array of Independent Module Based Solid State Drives

Solid state drives (SSD) are usually built using a NAND flash memory array. An SSD controller manages datastreams stripped to multiple flash memory channels. The device could be regarded as a level-0 structure of redundant array of independent disk (RAID), the technical term for a disk array system. This typical SSD controller architecture is called an intrinsic RAID (iRAID). An iRAID-based SSD controller has to execute sophisticated wear-leveling algorithms and dynamically calculate the lifespan of each flash memory chip as well as run error correction coding. redundant array of independent module (RAIM) was proposed to simplify the SSD controller by applying a group of standardized memory modules instead of raw flash memory chips. One of the widely recognized memory modules is the embedded multi-media card (eMMC) module, which is a small component, typically with a ball grid array package, and is found in consumer applications. In the paper, we have described the methods needed to optimize wear-leveling in an array of eMMC modules and deduced a formula to evaluate and optimize the lifespan of an RAIM-based SSD. A silicon SSD controller was implemented to verify the analysis. The positive result revealed that the lifespan of the RAIM-based SSD could be improved in consumer-grade eMMC modules.

Demonstration of Unsupervised Learning With Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array

We investigate the characteristics of a synaptic imitation device using a thin-film transistor (TFT)-type NOR flash memory cell with a half-covered floating gate. The long-term potentiation (LTP) and long-term depression (LTD) required for the operation of the spike-timing-dependent plasticity (STDP) algorithm are implemented using the proposed pulse scheme. Unsupervised learning is successfully demonstrated by applying the STDP learning rule through software MATLAB simulation reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory array. We present the learning and recognition processes of $28\times28$ MNIST handwritten digit patterns. First, STDP learning in a single-neuron string ( $784\times1$ ) is investigated, after which STDP learning is demonstrated in a multineuron array ( $784\times10$ ) with a lateral inhibition function to demonstrate the ability of multipattern learning and recognition. Meanwhile, we investigate the key factors of STDP unsupervised learning. Finally, an approach is suggested to implement a hardware neural network using the conventional CMOS technology for STDP unsupervised learning as a visual pattern recognition system.

True Random Number Generation Using Read Noise of Flash Memory Cells

In this paper, we propose and demonstrate a novel technique for true random number generation using commercial off-the-shelf Flash memory. Flash memory cells are known to exhibit thermal noise and random telegraph noise during sensing of their threshold voltage. In order to extract this inherent noise properties of the Flash memory bits through a standard digital Flash memory interface, we utilize the program disturb and read noise characteristics, which are fundamental properties of all NAND Flash memory arrays. The proposed technique is experimentally demonstrated and evaluated using state-of-art Flash memory chips. The experimental evaluation shows that the proposed technique enables extraction of high quality, high throughput, controllable (or tunable), and temperature- and aging-tolerant random bits. The random bits generated by the proposed technique pass all tests in the National Institute of Standards and Technology statistical test suite. The advantages of the proposed technique are as follows: 1) it is cost-effective as it does not require any special circuitry or hardware modification; 2) it is tolerant to aging and temperature effects; 3) it is easy to implement in software and to deploy through software updates; and 4) it is widely applicable to all electronic devices utilizing modern NAND Flash memory chips.