Flash-based Field Programmable Gate Array Research Articles

Programming mechanism and characteristics of Sense-Switch pFlash cells

Sense-Switch pFlash is a common floating gate switching cell with the advantages of high integration, natural field-edge total dose radiation hardness, and high reliability. It is the core configuration cell of the field-programmable gate array (FPGA), and it can be used to realize radiation-hardened flash-based FPGA circuits. This study investigates the programming mechanism of the Sense-Switch pFlash device with dumbbell structure based on 0.13 μm eFlash technology and analyzes the influences of the device's programming and erasing methods on the threshold characteristics, on/off-state characteristics, and retention characteristics of Sense-Switch pFlash cells. It is found that there are multiple mechanisms in the programming process. Additionally, under certain programming and erasing voltage conditions, the threshold voltage and driving current of programming/erasing state depend on the pulse width, meaning that a fixed pulse width leads to specific threshold voltage and driving current values in the programming and erasing modes, which is called the pulse width modulation effect (PWME). Multi-level storage can be well obtained to expand the application of the Sense-Switch pFlash in the field of computing-in-memory and brain-inspired computing.

SET characterization of 130 nm flash-based FPGA device

Low-power, flash-based field programmable gate arrays (FPGAs) have attracted significant attention in space electronic systems due to their re-programmability feature and non-volatility. In this study, we discussed a method for continuous and synchronous measurement of single event transient (SET) pulse widths in the ProASIC3 flash-based FPGA. The dedicated SET test system and irradiation set-up were implemented under heavy-ion irradiation. The SET generation cross-sections, pulse widths and capture characteristics in combinational logic chains were analyzed. The results indicated that the SET pulse width distribution exhibited a log-normal function and the SET capture probability linearly increased with the working frequency.

A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs

A comprehensive comparison between different design for testability (DFT) techniques for total-ionizing-dose (TID) testing of flash-based field-programmable gate arrays (FPGAs) is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan, clocked scan, and enhanced scan DFT techniques. The comparison is done using ISCAS'89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty in design bring-up, added delay by DFT logic, and robust testable paths in each technique. We verified the results of each technique experimentally using Microsemi ProASIC3 FPGA's and Cobalt 60 facility. The experimental results show a close total-dose failure level for all techniques when using worst-case test vectors (WCTVs) in total-dose testing of FPGA devices.

Reliable and Radiation-Hardened Push-Pull pFlash Cell for Reconfigured FPGAs

The base component of radiation-hardened flash-based field-programmable gate arrays (FPGAs) is a reconfigurable memory cell, which is reliable and has high driving current. A novel push-pull pflash cell was proposed in this article, which combined the advantages of indirect coupling and radiation-hardening. The proposed device consisted of two 2T-flash transistors and a pMOS transistor. The push-pull pflash cell was successfully fabricated using 90 nm technology. Through the indirect coupling of the floating gate (FG), the proposed push-pull pflash cell overcame the interference found in sense-switch pflash cells. Compared to conventional sense-switch pflash cells, the proposed push-pull pflash cell had superior driving current, reliability, and radiation-hardening. Band-to-band tunneling-induced hot-electron (BBHE) programming was used to realize ON state, while Fowler-Nordheim (FN) erasing was used to realize OFF state in the proposed device. The electrical properties of both states were characterized. The ON-state driving current and OFF-state leakage current were shown to be consistent. The uniformity of driving current under -1.2 V was below 3%. The proposed device was capable of being programmed/erased cyclically over 10,000 times, and it had a 10-year lifespan with ON/OFF-state stress at 25°C. Additionally, the proposed device was tolerant of total ionizing dose (TID) over 150 Krad(Si). The purposed push-pull pflash cell was suitable for applications in flash-based FPGAs.

Proton Beam Validation of a New Single Event Transient Mitigation Technique

A single event transient (SET) filtering technique for non-volatile field programmable gate arrays (FPGAs) are investigated experimentally using the AND-OR-Multiplexer SET filter technique. The technique combines AND – OR gate circuits in parallel with a two input multiplexer to provide a single circuit that can dissipate SETs irrespective of whether the input state is high or low. This paper presents the results of the experimental investigation, with the SET filter applied to various sequential circuit configurations in a commercial Flash-based FPGA, the 0.13-μm ProASIC3E product family (A3PE), by proton beam irradiation. Their implementation and evaluation in-beam show their efficiency in eliminating SETs and single event upsets (SEU) compared to unmitigated designs.

Reliability Analysis of Ethernet-Based Solutions for Data Transmission in the CERN Radiation Environment

The necessity for a radiation-tolerant communication link, compatible with a wide range of devices, has prompted the study of different solutions than those currently employed at CERN. With Ethernet being one of the most established communication protocols for commercial and industrial applications, most of the efforts were concentrated toward that direction. To evaluate the feasibility of using this protocol in the radiation environment of CERN, several Ethernet-based solutions have been implemented based on a system on chip (SoC), in which a flash-based field-programmable gate array (FPGA) and a $\mu $ controller coexist, making the system highly configurable. The proposed solutions are qualified at the system level using accelerated testing means, in order to compare their performances. The results of this study are then used to estimate the reliability of the different solutions using classic models, considering a variety of different installation scenarios inside the Large Hadron Collider (LHC) tunnel.

Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose

We introduce a methodology for identifying worst case test vectors (WCTVs) for delay failures induced by total dose in sequential circuits implemented in flash-based field-programmable gate arrays (FPGAs) using design-for-testability (DFT) techniques and path delay faults using commercially available DFT and automatic test pattern generation (ATPG) tools. We verified this methodology experimentally using Microsemi ProASiC3 FPGAs and Cobalt 60 facility. The experimental results show a significant impact on the total dose failure level when using WCTVs in total-dose testing of FPGA devices.

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs

Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden core of many applications especially in space and avionic fields where reliability is an important concern. In particular, for Flash-based FPGAs, when adopted in those applications, the main concern is radiation-induced voltage glitches known as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect. This tool has been applied to EUCLID space mission project including more than ten modules. The experimental results demonstrate the efficiency of the proposed tool.

Performances of typical high energy physics applications in flash-based field-programmable gate array under gamma irradiation

Recent field-programmable gate arrays (FPGAs) based on flash memories offer a high radiation tolerance. We discuss potential applications of the Microsemi IGLOO2 FPGAs in high energy experiments. We implement a 24 channel time-to-digital converter with a time binning of 0.78 ns and evaluate the performance. Differential and integral non-linearity is measured to be far below the time binning. The time resolution obtained is approximately 0.25 ns. The FPGA was exposed to gamma rays with a total ionizing dose of 300 Gy. The function of the configuration memory is monitored and the degradation of the performance on the ring oscillator and high-speed transceiver is measured. The errors during firmware download and verification of downloaded firmware have been observed at 110–120 Gy and 80–90 Gy, respectively. The functionality of the ring oscillator and high-speed transceiver remains up to about 200 Gy.

Radiation effects in reconfigurable FPGAs

Field-programmable gate arrays (FPGAs) are co-processing hardware used in image and signal processing. FPGA are programmed with custom implementations of an algorithm. These algorithms are highly parallel hardware designs that are faster than software implementations. This flexibility and speed has made FPGAs attractive for many space programs that need in situ, high-speed signal processing for data categorization and data compression. Most commercial FPGAs are affected by the space radiation environment, though. Problems with TID has restricted the use of flash-based FPGAs. Static random access memory based FPGAs must be mitigated to suppress errors from single-event upsets. This paper provides a review of radiation effects issues in reconfigurable FPGAs and discusses methods for mitigating these problems. With careful design it is possible to use these components effectively and resiliently.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

Fault Modeling and Worst-Case Test Vector Generation for Flash-Based FPGA’s Exposed to Total Dose

We analyzed the delay failure induced in flash-based field-programmable gate arrays (FPGAs) exposed to total-ionizing dose. We developed a novel cell-level fault model for such delay failure. We introduced a novel methodology for identifying worst case test vectors (WCTVs) for flash-based FPGA devices exposed to total-ionizing dose based on the developed fault model for delay failure. We introduced a novel methodology to identify WCTVs for flash-based FPGAs using commercially available design and automatic test pattern generation tools. We validated the delay fault model using Microsemi ProASIC3 FPGAs and Cobalt 60 facility. The experimental results also show significant impact on the total-dose failure levels when using WCTVs.

Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through ${{\rm V}_{\rm T}}$ Shift

Reliability test results of data retention and total ionizing dose (TID) in 65 nm Flash-based field programmable gate array (FPGA) are presented. Long-chain inverter design is recommended for reliability evaluation because it is the worst case design for both effects. Based on preliminary test data, both issues are unified and modeled by one natural decay equation. The relative contributions of TID induced threshold-voltage shift and retention mechanisms are evaluated by analyzing test data.

Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs**Supported by National Natural Science Foundation of China (11079045, 11179003 and 11305233)

Embedded RAM blocks (BRAMs) in field programmable gate arrays (FPGAs) are susceptible to single event effects (SEEs) induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes (ECCs), the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed, and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.

Experimental study on heavy ion single-event effects in flash-based FPGAs

With extensive use of flash-based field-programmable gate arrays (FPGAs) in military and aerospace applications, single-event effects (SEEs) of FPGAs induced by radiations have been a major concern. In this paper, we present SEE experimental study of a flash-based FPGA from Microsemi ProASIC3 product family. The relation between the cross section and different linear energy transfer (LET) values for the logic tiles and embedded RAM blocks is obtained. The results show that the sequential logic cross section depends not too much on operating frequency of the device. And the relationship between 0 → 1 upsets (zeros) and 1 → 0 upsets (ones) is different for different kinds of D-flip-flops. The devices are not sensitive to SEL up to a LET of 99.0 MeV cm2/mg. Post-beam tests show that the programming module is damaged due to the high-LET ions.

Single Event Latch-Up Hardening Using TCAD Simulations in 130 nm and 65 nm Embedded SRAM in Flash-Based FPGAs

In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number of SRAM cells included in the 3D structure significantly affects the SEL threshold. The number of SRAM cells needs to be optimized for accurate SEL prediction within a reasonable simulation time.The simulation results are validated using heavy ion and neutron data. After trade-off studies, process mitigation solutions are chosen to improve the SEL threshold in 65 nm and achieve immunity in neutron environment.

Study on FPGA SEU Mitigation for the Readout Electronics of DAMPE BGO Calorimeter in Space

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of the Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based field-programmable gate array (FPGA), of which the design-level flip-flops and embedded block random access memories (RAM) are single event upset (SEU) sensitive in the harsh space environment. To comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.

New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs

Single-event transients (SETs) remain a concern in field-programmable gate arrays (FPGAs) used for space applications. However, accurate measurement of SETs in FPGAs is challenging. This paper describes a calibrated circuit for on-chip measurement of SETs with a temporal precision better than one gate delay. In addition, a technique to measure the final effect of SETs in clocked, complex circuits is presented. Heavy-ion test results for a ProASIC3L FPGA are reported, highlighting a strong dependence between the VersaTile configuration and input signal state with the SET sensitivity and pulse propagation.

A Field-Programmable Gate Array (FPGA) TDC for the Fermilab SeaQuest (E906) Experiment and Its Test with a Novel External Wave Union Launcher

We developed a field-programmable gate array (FPGA) TDC module for the tracking detectors of the Fermilab SeaQuest (E906) experiment, including drift chambers, proportional tubes, and hodoscopes. This 64-channel TDC module had a 6U VMEbus form factor and was equipped with a low-power, radiation-hardened Microsemi ProASIC3 Flash-based FPGA. The design of the new FPGA firmware (Run2-TDC) aimed to reduce the data volume and data acquisition (DAQ) deadtime. The firmware digitized multiple input hits of both polarities while allowing users to turn on a multiple-hit elimination logic to remove after-pulses in the wire chambers and proportional tubes. A scaler was implemented in the firmware to allow for recording the number of hits in each channel. The TDC resolution was determined by an internal cell delay of 450 ps. A measurement precision of 200 ps was achieved. We used five kinds of tests to ensure the qualification of 93 TDCs in mass production. We utilized the external wave union launcher in our test to improve the TDC's measurement precision and also to illustrate how to construct the Wave Union TDC using an existing multi-hit TDC without modifying its firmware. Measurement precision was improved by a factor of about two (108 ps) based on the four-edge wave union. Better measurement precision (69 ps) was achieved by combining the approaches of Wave Union TDC and multiple-channel ganging.

An Ultralow-Power Wireless Camera Node: Development and Performance Analysis

This paper presents the design principles underlying the video nodes of long-lifetime wireless networks. The hardware and firmware architectures of the system are described in detail, along with the system-power-consumption model. A prototype is introduced to validate the proposed approach. The system mounts a Flash-based field-programmable gate array and a high-dynamic-range complementary metal-oxide-semiconductor custom vision sensor. Accurate power measurements show that the overall consumption is 4.2 mW at 3.3 V in the worst case, thus achieving an improvement of two orders of magnitude with respect to video nodes for similar applications recently proposed in the literature. Powered with a 2200-mAh 3.3-V battery, the system will exhibit a typical lifetime of about three months.