Fixed-point Digital Signal Processor Research Articles

Practical robust adaptive control on a fixed point digital signal processor

This paper addresses the development of a novel real-time Adaptive Controller which overcomes the difficulties associated with numerical ill-conditioning and 'bursting' phenomena. These problems arise as a result of truncation effects, mismodelling and lack of persistent excitation. The algorithm is implemented on a Texas Instruments TMS320C25 fixed point digital signal processor and the resultant Adaptive Controller is shown to be both practical and robust.

Techniques for improving the performance of CELP-type speech coders

Techniques for improving the performance of CELP (code excited linear prediction)-type speech coders while maintaining reasonable computational complexity are explored. A harmonic noise weighting function, which enhances the perceptual quality of the processed speech, is introduced. The combination of harmonic noise weighting and subsample pitch lag resolution significantly improves the coder performance for voiced speech. Strategies for reducing the speech coder's data rate, while maintaining speech quality, are presented. These include a method for efficient encoding of the long-term predictor lags, utilization of multiple gain vector quantizers, and a multimode definition of the speech coder frame. A 5.9-kb/s VSELP speech coder that incorporates these features is described. Complexity reduction techniques which allow the coder to be implemented using a single fixed-point DSP (digital signal processor) are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Implementation of a real-time mobile channel simulator using a DSP chip

The problem of implementing a real-time channel simulator that can be used to test mobile communications equipment in the laboratory is considered. The objective of the design is to replicate the statistical characteristics of the multipath fading environment on a single-chip, fixed-point 16-b digital signal processor (DSP). The simulator design permits the user to select the simulation parameters, including vehicular speed, carrier frequency, ratio between the line-of-sight component and the multipath component, and the variance of average power. The design is based on variable-sampling-rate DSP techniques, and offers a novel solution to suppress the aliasing terms at intermediate stages where access to analog filters is cumbersome and costly. >

An evaluation of Radon transform computations using DSP chips

The Radon transform and its inverse (a filtered backprojection) are receiving increasing attention for applications in image reconstruction. As data collection capabilities and image reconstruction algorithms have become more sophisticated, the computational intensity of these problems has drastically increased. Parallel processing techniques are being used to implement highspeed hardware designs that will speed up this computationally burdensome task. Parallel arrays of digital signal processing (DSP) chips may be used to compute the Radon transform and back-projection for high-speed image reconstruction. In this paper we describe computation of the Radon transform and back-projection using a parallel pipelined processor architecture of DSP chips and evaluate the accuracy of the computations and quality of reconstructed images. To justify the computational approach selected, alternative procedures for computation of the Radon transform and back-projection are described and their performance using the 32-bit fixed-point arithmetic of the selected DSP chips are compared. We present, evaluate, and compare the simulated performances of implementations of these procedures on two fixed-point DSP chips: the TI TMS32020 and the AT&T DSP16.

Transformationscodierung mit fester Bitzuteilung bei Audiosignalen

A Transform Codec has been developed to reduce transmission bandwidth or memory requirements for digital high-quality audio signals without perceivable degradation. Using fixed bit allocation the data rate can be reduced by a factor higher than five. The technique presented is based on the Discrete Fourier Transform and characterized by compactness and robustness against channel errors. For implementation a real time hardware system consisting of two different fixed-point digital signal processors has been designed.

Block floating-point implementation of digital filters using the DSP56000

The advantage of using block floating-point arithmetic as an alternative to fixed and floating-point arithmetic in the implementation of digital filters is considered. The block floating-point implementation of a second-order biquad digital filter structure using the Motorola DSP56000 fixed-point digital signal processor is described.

Design and implementation of a robust pitch detector based on a parallel processing technique

The design and implementation of a parallel-processing-based pitch detector is presented. Pitch information is extracted by performing pitch detection on four different waveforms derived from the speech signal. Pitch information from the four pitch-detection processes is then combined to determine a final pitch estimate. The performance of this pitch detector is evaluated on a large database and compared to other well-known pitch detection algorithms. It has been implemented in real time on a TMS32020 fixed-point digital signal processor as part of a 2.4 kb/s vocoder. A performance comparison of the real-time fixed-point implementation and a computer simulation are also given. The results show that the pitch detector performance is maintained in the real-time implementation mainly because the majority of the algorithm computations are integer arithmetic and logic-type operations. >