Fixed Oxide Charge Research Articles

The impact of sputtering pressure on the TiO2/p-Si interface and its implications for hole-blocking and photodetection

One convenient approach to minimize the surface recombination loss in Si is to passivate the surface dangling bonds by depositing a thin TiO2 layer on the bulk Si. Besides, the p-Si/TiO2 interface can initiate hole-blocking and facilitate efficient electron transport through the TiO2 layer; thereby, promoting the extraction of electrons for efficient onward utilization. In this context, the current investigation involves studying how the Ti3+ donor states, produced by deliberately introducing O-vacancies controlled by changing the plasma pressure in the RF-magnetron sputtering chamber during the growth of the TiO2 thin films, can change the material's Fermi level and work function and modify the band bending and band offset as well as the fixed oxide charge density in the p-Si/TiO2 heterojunction interface. The TiO2/p-Si interface has been studied through capacitance-voltage (C-V) analysis to determine the interface parameters such as fixed oxide charge, the density of interface traps, and the dielectric constant of TiO2. The studied hole-blocking property of the interface has been correlated to the photoresponsivity of the metal-oxide-semiconductor (MOS) structure. The MOS device fabricated at a pressure of 30 mTorr displays a large saturation current (15.95 μA cm–2) when subjected to a positive gate bias, facilitated by the relatively low conduction band offset (ΔEC ∼0.20 eV), significant positive fixed oxide charge (+1.18 ×1011 cm–2) and the interface trap density (1.03 ×1012 cm–2), which enhanced the transport of minority carrier electrons from the p-Si to the metal, resulting in a good photo responsivity ∼0.158 AW–1 and photo gain of ∼37.5 under white light illumination. Optimum hole-blocking and surface passivation characteristics of the TiO2/p-Si interface together may facilitate fabricating improved heterojunction Si solar cells.

Calibration of second harmonic generation technique to probe the field-effect passivation of Si(100) with Al2O3 dielectric layers

Optical second harmonic generation (SHG) can be employed to characterize the passivation quality of semiconducting material interfaces. The interface electric field (EDC) related to the existing charges at and near the interface, including the fixed oxide charges Qox, gives rise to the electric field induced second harmonic phenomenon. In this paper, we calibrate the SHG response for EDC measurement, using Al2O3/SiO2/Si(100) samples with different Qox. To perform this calibration, SHG and capacitance-voltage measurements (to access the electrical field of the samples) were made. The experimental results match well the simulated calibration curve, proving the potential of the SHG as stand-alone characterization technique for dielectric stacks on Si.

Study of silicon surface passivation by ZnOx/AlOx stack prepared using super-cycle approach in thermal ALD process

High quality surface passivating films are essential for high efficiency solar cells. In this work, we present our study about the silicon surface passivation performance of thermal atomic layer deposited (T-ALD) ZnOx/AlOx stack deposited using super-cycle approach. Super-cycle approach is composed of three cycles of DEZ-DI water system followed by one cycle of TMA-DI water system. The number of super-cycles is varied to change the film thickness. Excellent passivation with surface recombination velocity ∼ 7 cm/s was achieved under this study for hydrogen annealed films. The passivation mechanism is related to the saturation of defects by hydrogen after annealing and further improvement in fixed oxide charges by one order of magnitude (1010 to 1011 cm−2). Hydrogenation at the optimum temperature (450⁰C) involves the transport of hydrogen atoms towards the interface and their interaction with dangling bonds at the Si surface leading to the effective passivation. The optical transmittance of the film in the visible region of the spectrum is found to be >95 % for all the deposited films. XPS data reveals that deposited films are Al rich which is possible due to ligand exchange reactions during the growth process. Annealing of ZnOx/AlOx stacks in hydrogen ambient and their Al-rich behavior helps in the realization of good passivation performance. XPS study also shows that Al-O bond improves with film thickness. According to valence band spectra, a relative shift in Fermi level position with regard to the valence band improves band bending, which improves field effect passivation. Such high-quality ZnOx/AlOx passivating films may improve the device efficiency.

Boosting Kesterite Solar Cell Performance with Tantalum Oxide Passivation Layer and In Situ Formed Point Contacts

Kesterite solar cells often suffer from low open‐circuit voltage due to interface recombination. To address this, a passivation approach is explored using a dielectric layer between the absorber and buffer layer, coupled with a point contact structure. In this method, carrier transport is enabled through point contacts while effectively passivating regions covered by oxide. In this study, although forming point contacts on the front surface poses processing challenges, a novel solution is presented. Herein, in situ formed ZnS nanoparticles (NPs) during Cu2ZnSn(S, Se)4 (CZTSSe) absorber fabrication is utilized as a nanomask for front surface point contacts. A thin TaOx layer, acting as the passivation layer, is deposited over the CZTSSe surface with ZnS NPs by using atomic layer deposition (ALD). The selective removal of these NPs by deionized water soaking creates size‐controlled point contacts without damaging the absorber surface. In this approach, the first successful implementation of TaOx in enhancing CZTSSe solar cell efficiency, which jumps from 6.17% to 9.02% due to this strategy, is marked. The passivation mechanism involves sodium attraction during ALD, reduced interface defects, and the generation of positive fixed oxide charges. In this innovative method, not only solar cell efficiency is improved but new insights are also provided into using secondary phases as nanomasks in interface engineering.

Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors

In this work, models of p-type CuO metal-oxide- semiconductor (MOS) capacitor and thin-film transistors (TFTs) are established using numerical simulation tools and compared with experimental data, to investigate the impact of a passivation layer on the TFT subthreshold behavior. Simulated transfer curves and hole concentrations of back-gated CuO TFT with 10 μm channel length confirm the experimental observation of buried-channel and accumulation-mode conduction mechanisms. The subthreshold behavior is analyzed with HfO2 passivation on the top CuO surface varying the densities of fixed oxide charge and interface states, as well as the thickness of the CuO film. The simulation results demonstrate a significant potential improvement of the subthreshold slope and on/off current ratio, mainly thanks to the optimization of the fixed oxide charge densities.

Charge trapping and photovoltaic characteristics in monocrystalline silicon solar cells employing molybdenum oxide and copper oxide stacked hole-selective contacts

A hole-selective contact (HSC) composed of stacked layers of molybdenum oxide (MoOx) and copper oxide (CuOx), called MOCOSL, has been proposed as passivation booster for screen-printed monocrystalline silicon solar cell (SMSC) applications. The passivation quality of MOCOSL is investigated by characterizing its charge trapping properties, including fixed oxide charge (Qf) and interface trap density (Dit). The conversion efficiency (CE) of SMSCs is improved by MOCOSL, resulting in an increase from 20.66% to 21.76%. This improvement is attributed to an increase in the negative Qf and a decrease in Dit, which result in an increase in the open circuit voltage (Voc) and short circuit current (Jsc). Specifically, the number of negative Qf is increased by MOCOSL, which helps to reduce the recombination of charge carriers.

Realizing improved performance of metal-insulator-semiconductor diodes with high-k MgO/SiOx stack

With the development of metal-insulator-semiconductor (MIS) field-effect transistors, the thickness of silicon dioxide (SiO2) must be scaled down; however, it causes a large gate leakage current and a low on/off current ratio. Magnesium oxide (MgO) exhibits a dielectric constant as high as 11.2, which is about three times larger than that (3.9) of SiO2; thus the thickness of MgO can be three times greater than that of SiO2 and significantly reduces the gate leakage current. Nevertheless, a large lattice mismatch (22.5%) exists between MgO and Si materials. In the study, the MgO/SiOx stack dielectrics are employed to suppress the large lattice mismatch and improve the performance of MIS diodes. The MgO/SiOx stack largely reduces the oxygen vacancy of MgO from 75% to 52.3%; also the fixed oxide charge and interface trap charge density are drastically decreased from 1.3 × 1012 and 1.8 × 1013 to 8.2 × 1011 cm−2 and 7.8 × 1012 cm−2eV−1, respectively. Compared to the MIS diodes with a single MgO, the MgO/SiOx stack dielectrics suppress the gate leakage current by about two orders in MIS diodes; hence the rectification ratio is enhanced from 114 to 1032 at ±2V. Band-diagram shows that Fowler-Nordheim tunneling occurs at a high reverse-bias voltage, and the barrier height increases from 0.18 to 0.42 eV in the MIS diodes with single MgO and MgO/SiOx stack dielectrics, respectively. Nevertheless, the MIS diodes operate through a direct tunneling at low reverse-bias voltages.

Flatband voltage in MOS structures for spatial fixed oxide charge distributions

Flatband voltage in MOS structures for spatial fixed oxide charge distributions

Gamma-radiation hardness and long-term stability of ALD-Al2O3 surface passivated Si

Al2O3 has emerged as the surface passivation material of choice for p-type silicon in photovoltaics and has also become a candidate for passivating Si-based radiation sensors. However, the surface passivation of Al2O3 has been shown to degrade when exposed to gamma-radiation, making it of interest to determine methods of depositing Al2O3 that minimize the radiation-induced degradation on the surface passivation. In this study, we investigate the long-term stability and gamma-radiation hardness of Al2O3 prepared using the TMA+H2O+O3 precursor combination and how the pretreatment, the deposition temperature, and the film thickness affect the density of interface states, Dit, and fixed oxide charge, Qfix, before and after gamma-irradiation. We find that the surface saturation current density, J0s, of silicon passivated by Al2O3 increases after annealing but stabilizes over time depending on the Al2O3 thickness. Samples with thicknesses of <20 nm stabilize within hours, while those with >60 nm stabilize over days. J0s stabilizes at lower values with increased Al2O3 thickness. After exposure to 1 Mrad gamma-radiation, the samples still exhibit low Dit and high Qfix, with the best performing sample having a Dit of 1.5 × 1010 eV−1 cm−2 and a Qfix of −3.1 × 1012 cm−2. The deposition temperature appears to indirectly affect radiation hardness, owing to its impact on the hydrogen concentration in the film and at the Si–SiOx–Al2O3 interface. Lifetime measurements after irradiation indicate that Al2O3 still passivates the surface effectively. The carrier lifetime and Qfix can largely be recovered by annealing samples in O2 at 435 °C.

Effects of post metallization annealing on Al2O3 atomic layer deposition on n-GaN

The chemical, physical and electrical properties and the robustness of post metallization annealed Al2O3 atomic layers deposited on n-type GaN are investigated in this work. Planar metal insulator capacitors are used to demonstrate a gate-first with following ohmic contacts formation at elevated temperature up to 600 °C process flow. X-ray photoelectron spectroscopy indicates that no new bonds in the Al2O3 layer are formed due to exposure to the elevated annealing temperature. X-ray diffraction measurements show no crystallization of the oxide layer. Atomic force microscopy shows signs of degradation of the sample annealed at 600 °C. Electrical measurements indicate that the elevated annealing temperature results in an increase of the oxide depletion and the deep depletion capacitances simultaneously, that results in a reduction of the flat band voltage to zero, which is explained by fixed oxide charges curing. A forward bias step stress capacitance measurement shows that the total number of induced trapped charges are not strongly affected by the elevated annealing temperatures. Interface trap density of states analysis shows the lowest trapping concentration for the capacitor annealed at 500 °C. Above this temperature, the interface trap density of states increases. When all results are taken into consideration, we have found that the process thermal budget allows for an overlap between the gate oxide post metallization annealing and the ohmic contact formation at 500 °C.

Charge carrier motion and effect of fixed oxide charge in a microstructured silicon radiation detector

Signal formation in a microstructured semiconductor neutron detector is more complex than in planar diode geometry. Three-dimensional microstructures are laterally smaller than the ionization cloud length, and the electric fields may be weak enough to exhibit plasma time effects. This work is the first detailed treatment of charge carrier motion in these complex semiconductor devices to replicate the time profile and signal magnitude. Simulations were performed using COMSOL Multiphysics to investigate various parameters that affect the propagation of the charge cloud. It was observed that the size of the simulated three-dimensional structure had an impact on the induced current pulse, indicating the importance of simulation geometry optimization to accurately simulate charge cloud expansion. COMSOL Multiphysics was used to replicate accurate charge creation profiles using energy deposition information imported from radiation transport codes. A detailed simulation methodology is presented to benchmark preamplifier event pulses along with complexities in modeling the charge carrier motion along the etched microstructured trenches with Si–SiO2 boundary conditions, including fixed oxide charge and interface trapping.

The Mechanistic Determination of Doping Contrast from Fermi Level Pinned Surfaces in the Scanning Electron Microscope Using Energy-Filtered Imaging and Calculated Potential Distributions

Abstract Secondary electron (SE) doping contrast in the scanning electron microscope is correlated with Fermi level pinned surfaces of Si samples prepared using HF-based wet-chemical treatment or focused ion beam (FIB) micromachining en route to quantitative dopant profiling. Using energy-resolved SE imaging techniques and finite-element analyses of surface states and surface junction potentials, we clarified the surface band-bending effects post-NH4F-treatment, consistent with brighter p-contrast from degenerately doped (>1019 cm−3) regions. In general, SE spectromicroscopy scan measurements unambiguously indicated heavy suppression of patch fields, while the empirical discovery of scan frequency-modulated contrast inversion due to Chee et al. [Springer Proceedings in Physics, 120, pp. 407–410 (2008)] is ascribable to competing fixed oxide charge and dynamic charge injection phenomena (particularly at dwell times >29 μs). Leveraging numerical simulations of electric potentials and variable-voltage experimental data, the theoretical model based on amorphization damage-mediated Fermi level pinning is elucidated for Ga+ FIB-processed site-specific doping contrast on patch field-free surfaces. This work successfully argues against the notion that doping contrast ultimately or exclusively entails patch fields or adventitious metal–semiconductor contacts.

Surface-potential-modulated piezoresistive effect of core–shell 3C-SiC nanowires

The effect of surface potential on the carrier mobility and piezoresistance of core–shell silicon carbide nanowires (SiC NWs) was investigated to realize small and sensitive SiC-microelectromechanical systems sensors. The p-type cubic crystalline SiC (3C-SiC) NWs were synthesized via the vapor–liquid–solid method and coated with silicon dioxide (SiO2) or aluminum oxide (Al2O3) dielectric shells to form core–shell structured NWs with different surface potentials. Four-point bending devices (FBDs) with a field-effect transistor (FET) configuration integrating a single core–shell 3C-SiC NW as the FET channel were fabricated to apply an additional electric field and strain to the core–shell 3C-SiC NWs. The fixed oxide charge densities of the SiO2 and Al2O3 shells showed positive and negative values, respectively, which were equivalent to electric fields of the order of several hundred thousand volt per centimeter in absolute values. In the core–shell 3C-SiC NWs with originally low impurity concentrations, the electric field induced by the fixed oxide charge of the shells can determine not only the electrical conduction but also the charge carriers in the NWs. Bending tests using the FBDs showed that the piezoresistive effect of the SiO2-coated NW was almost the same as that of the as-grown 3C-SiC NW reported previously, regardless of the gate voltage, whereas that of the Al2O3-coated NW was considerably enhanced at negative gate voltages. The enhancement of the piezoresistive effect was attributed to the piezo-pinch effect, which was more pronounced in the NW, where the carrier density at the core–shell interface is enhanced by the electric field of the dielectric.

Detailed Analysis on Determining Effective Dose for Various JTE-Based Edge Terminations Utilized on 4H-SiC Power Devices

The article discusses the impact of thermal oxidation process conditions on the implanted junction-termination-extension (JTE) dose using various edge termination structures for 1700 V rated 4H-silicon carbide (4H-SiC) power devices. During the formation of gate oxide (Gox) via thermal oxidation, the surface of the SiC area is also consumed, resulting in a silicon dioxide layer. The surface consumption from the Gox process can significantly alter the blocking capabilities of the JTE-based edge termination structures due to a change in the ``effective'' dose. In addition, the fixed oxide charge and activation ratio can also fluctuate the charge in the JTE region. Therefore, all these factors should be considered when designing JTE-based edge terminations for 4H-SiC devices. Investigation of various edge termination structures such as single zone JTE (SZ-JTE), ring-assisted JTE (RA-JTE), multiple floating zone JTE (MFZ-JTE), Hybrid-JTE, and floating field rings (FFRs) allowed the identification of determining process steps. Detailed analysis of the effective JTE dose is reported by examining experimental and simulation results.

Post-annealing treatment in improving high dielectric constant MgO-based metal-oxide-semiconductor diodes

Metal-oxide-semiconductor (MOS) diodes with a high dielectric constant magnesium-oxide (MgO) insulating layer were fabricated using a magnetron radio frequency sputtering system. MgO has a high dielectric constant of approximately 11.2, which is three times higher than the dielectric constant (3.9) of silicon dioxide (SiO2), thereby ensuring a three times thicker gate oxide and reducing gate leakage current while maintaining the same capacitance density. Post-annealing treatment was employed on the MgO film to study how annealing treatment affects the electrical characteristics of MOS diodes. It was observed that the post-annealing treatment of MgO effectively diminished the gate leakage current by approximately one order, thereby increasing the rectification ratio from 8.5 × 103 to 6.8 × 104 for the MOS diodes with as-deposited and post-annealed MgO. In contrast to the MOS diodes with as-deposited MgO, the post-annealing treatment of MgO significantly decreased the flatband voltage shift from 7.8 to 1.3 V and reduced the fixed oxide charge density from 1.3 × 1012 to 2.3 × 1011 cm−2; also, the interface trap charge density was suppressed from 1.8 × 1013 to 3.2 × 1012 cm−2 eV−1. Large quantities of fixed oxide charge attracted more electrons accumulated at the Si surface, which decreased the barrier height from 0.85 to 0.81 eV for the MOS diodes with post-annealed and as-deposited MgO. Moreover, x-ray photoelectron spectroscopy showed that the oxide charges were caused by the defects inside MgO, particularly oxygen vacancies. The oxygen vacancies were compensated by the oxygen atoms introduced from the air during the post-annealing treatment.

(Digital Presentation) Characterization of Passivation Dielectrics on Silicon Through Second Harmonic Generation: Effect of Fixed Charge

This paper presents the characterization of alumina passivation layers using second harmonic generation (SHG). Based on nonlinear optics, the technique has the advantage of being rapid and non-destructive, especially for thin oxide layers. For the materials under study, the SHG is sensitive to the electronic and structural properties of the interface, particularly to the interfacial electric field (Edc), and thus allowing to characterize fixed oxide charges (Qox) in the oxide and interface traps density (Dit). Time-dependent SHG (TD-SHG) is firstly used here to probe samples with various Dit and a total oxide charges (Qtot), previously extracted using corona oxide characterization of semiconductor (COCOS). The measurement conditions are adjusted to focus on the impact of the fixed charges on the SHG signal. A more detailed analysis of the SHG versus input polarization is conducted in both experiments and simulations and it shows coherent evolution tendencies with the oxide charge.

Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula>) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.

Hidden surface channel in two-dimensional multilayers

Numerous carrier scatterers, such as atomic defects, fixed oxide charges, impurities, chemical residues, and undesired surface adsorbates, including oxygen and water molecules, strongly degrade the carrier mobility of atomically thin two-dimensional (2D) materials. However, the effect of surface adsorbates and surface oxidation on the carrier density profile along the thickness of 2D multilayers is not well known, particularly for a substantial interruption in the formation of the top-surface channel. Here, we uncover a hidden surface channel in p-type black phosphorus and n-type rhenium disulfide multilayers originating from undesired ambient adsorbates and surface oxides that not only populate hole density (or reduce electron density) but also suppress carrier mobility. The absence of a second peak in the transconductance curve under ambient conditions indicates the disappearance of the top-surface channel inside the 2D multilayers, which is a possible indicator for the cleanliness of the top surface and can be used in gas sensor applications. Moreover, the negligible variation in the drain bias polarity-dependent turn-on voltage for the bottom channel under ambient conditions validates the exclusive contribution of surface adsorbates to the formation of the top channel in 2D multilayers. Our results provide a novel insight into the distinct carrier transport in 2D optoelectronic devices and diverse sensors.

Preliminary benchmarks and analysis of boundary conditions in a trenched microstructured silicon radiation detector

Microstructured neutron detectors have the benefit of enhanced neutron detection efficiency as compared to planar devices, achieved by etching 6LiF-filled trenches on the top surface of a silicon PIN diode. This sensor geometry results in a complex electric field distribution and depletion characteristics within the diode under reverse bias. For the first time on record, the effects of a fixed oxide charge on the microstructured device depletion characteristics and mobile carrier transport is investigated. Prototype detectors were fabricated with non-conformal surface doping. Capacitance voltage and current voltage measurements were performed for these prototypes and compared with COMSOL Multiphysics simulations. A spectral response from an 241Am alpha particle source was acquired and analyzed. It was found that monoenergetic alpha particles produce three prominent peaks in the pulse height spectrum output by the device. The peaks were confirmed by simulations to correlate with dead layers and incident trajectories into the microstructure. It was also found that significant differences in pulse rise time result, corresponding with events arriving in a low-field region in the fins and a high-field region in the bulk. Geant4 was utilized for radiation transport, interaction modeling, and benchmarking the spectral data. The results of this simulation work provide confidence in the ability to attain and benchmark electrical characteristics and spectral data for semiconductor radiation detectors employing complex microstructures.

Characterization of thin Al2O3/SiO2 dielectric stack for CMOS transistors

This paper systematically investigates the electrical properties of thin Al2O3/SiO2 (with a target equivalent oxide thickness of 4.9 nm) as gate dielectric stack in the metal–oxide–semiconductor (MOS) capacitor. Different deposition techniques, i.e. thermal oxidation, thermal atomic layer deposition, and plasma-enhanced atomic layer deposition, are employed in the fabrication of MOS capacitors. The second derivative, Terman and conductance methods are used to extract the fixed oxide charges and interface trap densities in the MOS capacitors. Our results demonstrate that the Al2O3/SiO2 stack presents better performance in terms of negative fixed oxide charges and low interface trap density compared with the single-layer SiO2 with the similar equivalent oxide thickness about 3.9 nm. Furthermore, to evaluate the reliability of the Al2O3/SiO2 gate dielectric stack, the leakage current is analyzed. Contributions from Pool-Frenkel emission, trap-assisted tunneling, and Fowler-Nordheim mechanisms to the leakage current are detailed. Our results indicate that Al2O3/SiO2 gate dielectric stacks fabricated by plasma-enhanced atomic layer deposition Al2O3 and thermal SiO2 feature the lowest leakage current.