Characterization of thin Al2O3/SiO2 dielectric stack for CMOS transistors

Abstract

This paper systematically investigates the electrical properties of thin Al2O3/SiO2 (with a target equivalent oxide thickness of 4.9 nm) as gate dielectric stack in the metal–oxide–semiconductor (MOS) capacitor. Different deposition techniques, i.e. thermal oxidation, thermal atomic layer deposition, and plasma-enhanced atomic layer deposition, are employed in the fabrication of MOS capacitors. The second derivative, Terman and conductance methods are used to extract the fixed oxide charges and interface trap densities in the MOS capacitors. Our results demonstrate that the Al2O3/SiO2 stack presents better performance in terms of negative fixed oxide charges and low interface trap density compared with the single-layer SiO2 with the similar equivalent oxide thickness about 3.9 nm. Furthermore, to evaluate the reliability of the Al2O3/SiO2 gate dielectric stack, the leakage current is analyzed. Contributions from Pool-Frenkel emission, trap-assisted tunneling, and Fowler-Nordheim mechanisms to the leakage current are detailed. Our results indicate that Al2O3/SiO2 gate dielectric stacks fabricated by plasma-enhanced atomic layer deposition Al2O3 and thermal SiO2 feature the lowest leakage current.