Finite Impulse Response Filter Architecture Research Articles

Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures.

Background: This paper presents an efficient two-dimensional (2-D) finite impulse response (FIR) filter using block processing for two different symmetries. Architectures for a general filter (without symmetry) and two symmetrical filters (diagonal and quadrantal symmetry) are implemented. The proposed architectures need fewer multipliers because of the symmetry of the filter coefficients. Methods: A distributed arithmetic (DA)- based multiplication method is used in the proposed architecture. A dual-port memory-based lookup table (DP-MLUT) is used in the multiplication instead of lookup-table (LUT) to reduce the area and power of the FIR filter. The filter's throughput is increased by using block processing. Memory reuse and memory sharing methods are introduced, which reduces the need for many registers and hence the circuit complexity. The architectures are written in Verilog Hardware Description Language and synthesized using Genus Synthesis tool-19.1 in 45nm technology with a generic library of Cadence vendor constraints. The synthesis tool generates the area, delay, and power reports. Power consumption of architectures is calculated with an image size of 64 X 64 and at 20 MHz frequency. Results: Compared to existing architectures, the synthesis results show improvements in power, area, area delay product (ADP), and power delay product (PDP). The proposed MLUT-based 2-D block Quadrantal Symmetry Filter (QSF) for length 8 with block size 4 consumes 58.94% less power, occupies 59.5% less area, 48.44% less ADP and 47.78% less PDP compared to best existing methods. Conclusions: A novel DA-based 2-D block FIR filter architecture with various symmetries is realized. Symmetry is incorporated into the filter coefficients to minimize the number of multipliers. The LUT size is optimized by odd multiples or even multiples storage techniques. Also, the overall area of the architecture is decreased by DP-LUT-based multipliers. The proposed filter architecture is area-power-efficient. It is best suited for applications that have fixed coefficients.

Very large scale integration implementation of efficient finite impulse response filter architectures using novel distributed arithmetic for digital channelizer of software defined radio

AbstractAlways an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software‐defined radio (SDR). In this paper, a block‐based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look‐up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT‐based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)‐based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area‐delay product (ADP), and power delay product (PDP) are evaluated and compared with state‐of‐the‐art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC‐DA‐based filter architecture than the conventional DA‐based filter architecture, respectively.

High-performance, energy-efficient, and memory-efficient FIR filter architecture utilizing 8x8 approximate multipliers for wireless sensor network in the Internet of Things

IoT uses wireless sensor networks (WSN) to deploy many sensors to track environmental and physical parameters. The WSN measurements are frequently contaminated and altered by noise. The noise in the signal increases the sensor node’s computation and energy utilization, resulting in less longevity of the sensor node. The Finite Impulse Response (FIR) filter is commonly employed in WSN to pre-process sensed signals to remove noise from the sensed signals using delay elements, multipliers, and adders. Traditional multiplier-based FIR filter designs result in hardware-intensive multipliers that consume a lot of energy, and area and have low computation speed. These drawbacks make them unsuitable for IoT-based WSN systems with stringent power efficiency necessities. Approximate computing enhances the energy efficiency of an FIR filter. Arithmetic circuits utilizing approximate computing improve the hardware performance, with some loss of accuracy to save energy utilization and boost speed. A novel approximate multiplier architecture employing a fast and straightforward approximation adder is proposed in this study. Approximate multiplier M1 using OR gate and approximate multiplier M2 using proposed approximate adders are compared. The proposed approximate adder is suited for building an adder tree to accumulate partial product (PP) because it is less complicated than traditional adders. Compared to a one-bit-full adder, the critical path delay (CPD) is reduced significantly in the proposed methods. The accuracy comparison of M1. M2 and Wallace tree using the normalized mean error distance (NMED), the mean relative error distance (MRED), the maximum error (ME), and the error rate (ER) with the number of bits utilized for reducing error. For the area (delay) optimized circuit, when the bit used is 4, the delay is 0.4 ns for M1, 0.43 ns for M2, and 1.08 ns for the Wallace tree multiplier. For the delay (area) optimized circuit, when the bit used is 4, the delay is 0.16 ns for M1, 0.16 ns for M2, and 0.40 ns for the Wallace tree multiplier. To more accurately evaluate performance at the circuit level, the PDP and ADP are computed. The NMED, MRED, ME, and ER versus PDP and ADP are computed. The proposed multipliers M1 and M2 are compared with existing approximate multipliers. When an equivalent MRED, NMED, or ER is taken into account, M1 has the smallest ADP and PDP among other multipliers. The very low likelihood of a significant ED occurring is indicated by the small values of NMED and MRED in M1 and M2. The proposed solutions effectively reduce delay, area, and power while maintaining increased accuracy and performance.

Low power residue number system using lookup table decomposition and finite state machine based post computation

In this paper, memory optimization and architectural level modifications are introduced for realizing the low power <span lang="EN-US">residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.</span>

A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers

In this paper, a novel block-based generic filter bank architecture is proposed for various Two Dimensional (2D) symmetry Finite Impulse Response (FIR) filers. It is implemented to prune the area, storage memory, and power consumption of the filter bank. Four 2D symmetrical FIR filter architectures are implemented and explored along with a general filter (without symmetry). The symmetry in coefficients of the filter reduces the number of multiplier blocks (most power-hunger blocks) required for the structure. Hence, a major part of the total power consumption is decreased. Block processing is introduced to improve the throughput of the filter bank. The memory sharing and memory reuse concepts are incorporated to reduce the storage memory of the entire filter bank. Finally, the conventional multiplication process is replaced with memory-based dual-port Look-Up-Table (LUT)-Distributed Arithmetic (DA) multipliers to minimize the power and area of each sub-filter of the filter bank. A generic filter bank architecture is implemented and synthesized in CMOS 45 nm generic library using Genus tools and physical design is carried out by Innovus tools from Cadence. The final layout of the design is generated using proper floor planning, placement, and routing in physical design. The results are compared with the state-of-art works of 2D FIR filters. The significantly improved results are reported in terms of area, power, delay, and memory.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

AbstractThe very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Abstract The digital Finite Impulse Response (FIR) is extensively used in numerous Signal Processing applications, ranging from wireless communication to video and image processing. The digital filter fundamentally consists of adder, multiplier and delay element. Multiplier is a vital and hard building block in FIR filter. Numerous methods have been described in the study to execute Field Programmable Gate Array (FPGA) in digital FIR filter. Due to conventional multiplier architectures more power exhaust in the existing FIR filter architecture. In the multiplier section partial product generation consume more power. In proposed work, the implementation of 16-Tap FIR Filter design is performed with Radix-4 Booth Multiplier using Improved Booth Recoding Algorithm. The proposed multiplier architecture helps to minimize the number steps in multiplication and also in digital circuits decrease the propagation delay. Finally getting better performance for area, delay and power consumption is applied in these architecture to the FIR filter. FPGA synthesis tools produces the implementation results based on that performance evaluation done. Compared to FIR filter with traditional multiplier, results clearly indicate that by using Radix-4 Booth Multiplier with Improved Booth Recoding Algorithm of FIR filter attains better performance in power, resource utilization and area. By employing Radix-4 Booth Multiplier using Improved Booth Recoding Algorithm in FIR filter, power and capacity is condensed by 52.27 % and 22.20% individually when compared to traditional FIR filter. The results show that the Improved Booth multiplier-based FIR (radix-4) filter leads to smallest power and area. For communication purpose, FIR filter is also applicable.

High performance hardware design of compressor adder in DA based FIR filters for hearing aids

Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the different types of hearing loss, it is necessary to selectively amplify sounds at required frequencies. The main aim of the hearing aid is to selectively remove the noise signal such that the processed sound matches ones audiogram. To achieve this, the decimation filter in hearing aids can be design using multiplier less architecture which should be able to adjust sound levels at arbitrary frequencies within a given spectrum. In hearing aids, decimation filter plays a key role. This paper presents a low complexity design of a digital finite impulse response (FIR) filter for digital hearing aid application. This paper proposed approximate 4:2 compressor adders in memory less DA based FIR filter architecture. In DA architecture the area of the ROM increases gradually when filter order is increased. Memory less DA is designed using compressor adders is a solution to decrease the power consumption and area of the FIR filters and makes the area and power reduction for hearing aid application. The proposed DA based FIR filter architecture is synthesized on 90 nm technology using Synapsis Application Specific Integrated circuit design compiler. The proposed architecture has 45% reduction in area delay product when distinguish with systolic architecture and 10% less ADP when compare with OBC DA architecture. The proposed design is also implemented Field Programmable Gate Array and the results shows that the proposed architecture has less slices than best existing designs. The proposed architecture is used in decimation filter of hearing aids applications using matlab simulink, which removes the unwanted signal.

Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic

In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter using block least mean square algorithm (BLMS) based on systolic array architecture with parallel data processing units is presented. A high level of parallelism is observed in the proposed work, improving the efficiency of variable coefficient FIR structure. The parallel look-up tables (LUT) in combination with the shift accumulator emulate multiply and accumulate operations. In order to reduce the number of clock cycles, B parallel LUTs are used, where B is the coefficient size. The block processing in BLMS Adaptive FIR Filter of block length L gives L times high throughput. This structure accepts block of input samples and generates block of output in each clock cycle. It requires less number of registers for computing filter output response and weight increment vector as memory reuse concept is used for implementing registers. This structure doesn’t require multiplexer. The designed DA based FIR filter is implemented on FPGA. The implementation results shows that the manuscript presents a high speed and low power architecture. The proposed structure provides 17.3 times less power and 9.5 times increase in throughput when compared to existing designs.

Efficient FIR Filter Architecture using FPGA

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

Design and implementation of low complexity circularly symmetric 2D FIR filter architectures

This paper presents a low complexity two dimensional (2D) circular symmetric Finite Impulse Response (FIR) filter design and implementation of architecture. The optimized circular symmetric 2D FIR filter is designed using a modified Park–McClellan transformation method and filter coefficients are quantized using a canonical signed digit (CSD) binary number format. The CSD encoded coefficients are optimized to reduce the number of adder/subtractors using common subexpression elimination (CSE) algorithms. Based on the modified filter coefficients, the two structures fully direct form and hybrid-II form 2D FIR filter architectures are implemented using CSD and CSD with Horizontal CSE and Vertical CSE techniques. The proposed architectures compared with the conventional symmetry 2D filters and state-of-the-art architectures in terms of area, power, and speed.

Heterogeneous Adder Based FIR Filter Design And Simulation

The finite impulse response (FIR) is one of the important filters in digital signal processing (DSP) as it responds for a finite duration and settles to zero on the finite time. Digital FIR filters are programmable in nature and its behavior can be understood with the help of the program and can be easily programmed for the memory of a processor. The digital filters can be replaced without change of the hardware or the external circuitry. The 7 tap FIR filter needs 16 numbers of multipliers and 9 adders which are used in parallel form. The paper focused on the chip design and implementation of the FIR filter with a decimal adder and heterogeneous adder is done using VHDL programming in Xilinx 14.2 ISE software and the same is synthesized on SPARTAN - 3E FPGA to verify the results. Moreover, the functional simulation is done in Modelsim 10.0 software. Hardware utilization parameters, combinational path delay, memory utilization parameters are directly extracted from the Xilinx software for FIR filter architecture based on decimal adder and heterogeneous adders. The comparative analysis of the FIR filter is done with heterogeneous adder architecture lead an area and delay efficient design for DSP applications

High throughput and energy efficient FIR filter architectures using retiming and two level pipelining

Abstract A methodology to improve the throughput and energy efficiency of finite impulse response (FIR) filters through the effective application of retiming and two-level pipelining is presented in this paper. Improving throughput and energy efficiency of the filter while minimizing latency and hardware complexity is a challenge to be addressed. Two-level pipelining bifurcate the multiplication and addition operations. Retiming is applied to break addition operation. The basic architecture of a 64-tap filter consists of 4-tap pipelined retiming delay generation sub filter (PRF), a 4-tap pipelined sub filter (PSF) and 7 numbers of 8-tap pipelined sub filters. The critical path delay (CPD), effective latency (ELT), power-delay product (PDP) and area-delay product (ADP) of the proposed filter-1 is improved by 35%, 33.97%, 38.06% and 29.67% in comparison with the recent high throughput retimed filter (HTF1) for a filter length of 64. Cadence software with gpdk 45nm standard cell library is used for the design and implementation. An ECG denoising low pass filter is developed using the proposed filter-1 and performed simulation using modelsim.

Systolic Fir Filter using Bypass Multiplier

In DSP the most common function is Finite Impulse Response (FIR) filter which is realized in field Programmable gate Arrays (FPGAs). For efficient Very Large Scale Integration (VLSI) computation systolic FIR filter architecture has attractive models. High speed is the major concern for fast computation in real time Digital Signal Processing (DSP) applications. In conventional systolic FIR filter method uses general array multiplier structure which takes more time to compute the process with high design complexity with less power. To overcome this problem the systolic FIR filter utilizing Bypass Feed Direct Multiplier(BFDM) is proposed. The proposed method 16 tap systolic FIR parallel processing offers less delay with less design complexity which is used in image and signal processing applications. The proposed method is simulated using Xilinx ISE 12.4 ISE tool and the functions are evaluated by MODELSIM 6.3C.

Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

In recent years, Finite Impulse Response (FIR) filter plays a major role in signal processing applications. Earlier many research papers are described the different types of FIR filter design. But, none of the paper explained about signal denoising application with an effective multiplier design. In this paper, Vedic Design - Carry Lookahead Adder FIR filter architecture is introduced to perform the FIR filter operation with Electro Cardiogram (ECG) signal de-noising application. By usingthe MATLAB program, the input ECG signal is read and Additive White Gaussian Noise (AWGN) is added to the input signal. The denoising process is implemented in Verilog and the obtained output is written in text files. For de-noising the signal, the binary text values are read in MATLAB. With the help of Verilog code, FPGA performance (LUT, flip flop, slices, and frequency) and ASIC performance (area, power, and delay) are evaluated. For ASIC implementation, 180 nm and 45 nm technology are used and for FPGA implementation Virtex-4, Virtex-5, and Virtex-6 devices are used to evaluate the performance. The Mean Square Error (MSE), Bit Error Rate (BER), and Signal to Noise Ratio (SNR) performance are calculated from the de-noised signal. In 180 nm technology, 42.39% of the area, 29.53% of delay, 43.89% of APP, 70.41% of ADP reduced in VD-CLA-FIR. In 45 nm technology, 13.2% of the area, 32.25% of the delay, 24.37% of APP, and 39.02% of ADP reduced in VD-CLA-FIR method compared to the conventional methods.

Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation

We present an efficient multichannel finite impulse response (FIR) filter that uses the lookup-table (LUT) method. The size of the LUT is reduced by a factor of 8 over conventional LUTs by using Booth recoding, odd-multiple storage, and antisymmetric-product coding (APC) methods. The proposed multichannel FIR filter architecture provides up to 35% reduction in the power-delay product (PDP) over the existing architectures. The proposed strategy could be very useful for applications relating to IEEE Standard 802.15.4.

Design and implementation of least mean square algorithm for a new reconfigurable FIR filter architecture

Nowadays, the communications and computations has been performed by Digital Finite Impulse Response (FIR) filter. FIR filter is predominantly used in DSP applications for efficient implementations. FIR filter is able to declare a firm linear phase frequency characteristic with any type of amplitude frequency characteristic in a DSP system. A reconfigurable FIR filter architecture has been implemented using Least Mean Square (LMS) algorithm in the proposed scheme. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method has been implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.

Design of FIR Filter Using Different Multiplier Architecture For High Speed And Low Power Applications

Finite impulse response (FIR) filter is one of the key components in any DSP and communication systems. The output from the DSP processor is based on the FIR filter performance, so need an efficient FIR filter design, to achieve an efficient output. FIR Filter architecture contains many components; one of the key components is multiplier. Different types of multipliers are available in the digital circuits, but need an efficient multiplier design to get efficient filters. In the existing Vedic and Wallace tree multiplier was designed and implemented using verilogHDL. Partial products generation and reduction in the Wallace tree multiplier getting more complicated in speed and performance and also multiplier needs more gates to implement the design. To reduce the drawbacks in the existing system, to propose a new efficient multiplier named as Birecoder multiplier. It is one of the best multiplier in the digital circuit design. This multiplier overcomes the existing multiplier drawbacks by using multiplexer circuit. Multiplier is design by verilogHDL, after the design Wallace tree multiplier is compared with Birecoder, and analyzes the performance of the multiplier. Implement the design using Modelsim 6.3c and Xilinx ISE. Finally the designed multipliers are applied into the FIR filter, and show the best filter.

Scenario-Aware Dynamic Power Reduction Using Bias Addition

Typical modern communication systems operate over a wide dynamic range of signal strengths. We consider the approach of adding a bias as offset to reduce switching activity, and study the average bit toggle for signals with different distributions, as a function of signal span and the actual bias value added. From the analysis, we provide guidelines to choose an optimal bias value, based on the system scenario, to obtain the lowest power consumption. Simulation results confirm the accuracy of the theoretical analysis. Various finite-impulse response filter architectures are evaluated, and we propose suitable enhancements to them to enable improved power savings. We apply the bias addition technique and the proposed architectural enhancements to a wireless local area network digital receiver chain, and demonstrate that over 25% power savings can be achieved under different signal conditions.