WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Abstract

Abstract The digital Finite Impulse Response (FIR) is extensively used in numerous Signal Processing applications, ranging from wireless communication to video and image processing. The digital filter fundamentally consists of adder, multiplier and delay element. Multiplier is a vital and hard building block in FIR filter. Numerous methods have been described in the study to execute Field Programmable Gate Array (FPGA) in digital FIR filter. Due to conventional multiplier architectures more power exhaust in the existing FIR filter architecture. In the multiplier section partial product generation consume more power. In proposed work, the implementation of 16-Tap FIR Filter design is performed with Radix-4 Booth Multiplier using Improved Booth Recoding Algorithm. The proposed multiplier architecture helps to minimize the number steps in multiplication and also in digital circuits decrease the propagation delay. Finally getting better performance for area, delay and power consumption is applied in these architecture to the FIR filter. FPGA synthesis tools produces the implementation results based on that performance evaluation done. Compared to FIR filter with traditional multiplier, results clearly indicate that by using Radix-4 Booth Multiplier with Improved Booth Recoding Algorithm of FIR filter attains better performance in power, resource utilization and area. By employing Radix-4 Booth Multiplier using Improved Booth Recoding Algorithm in FIR filter, power and capacity is condensed by 52.27 % and 22.20% individually when compared to traditional FIR filter. The results show that the Improved Booth multiplier-based FIR (radix-4) filter leads to smallest power and area. For communication purpose, FIR filter is also applicable.