Design of FIR filter using novel pipelined bypass multiplier

Abstract

The vigorous growth in portable multimedia devices and communication system has increased the demand for area and power efficient high-speed Digital Signal Processing (DSP) system. Usage of digital Finite Impulse Response (FIR) filter is one of the prime block in DSP. Digital multipliers and adders are the most critical arithmetic functional units in FIR filters and also decides the performance of whole system. This research proposes a novel pipelined architecture of high-speed bypass multiplier which utilizes the bypassing method to minimize the switching activities and incorporates novel pipelining technique for improving its performance. Low-power and area-efficient register using pulsed latches added instead of flip-flops in the novel pipelining technique. A comparison between various bypass multipliers with pipeline in terms of delay, power and area utilization were also done in this work. Carry-Look ahead Adder (CLA) is used for addition operation which uses fastest carry generation technique to increases speed by reducing the time required to fix carry bits in ripple carry adder. By employing the proposed novel pipelined high-speed bypass multiplier and carry-look ahead adder, a digital FIR filter with length of 8-tap and 16-tap has been designed which results in a delay reduction of 52% and 33.2% respectively over the conventional method. Similarly, the power consumption analysed for the 8-tap and 16-tap FIR Filter circuit and obtained power saving of 39.7% and 28.7% respectively with reduction in area of 12.1% and 20.4% respectively is better compared to the non-pipelined technique.