FinFET Technology Node Research Articles

Efficacy of Spatial and Temporal RHBD Techniques at Advanced Bulk FinFET Technology Nodes

Single-event (SE) performance of a variety of radiation-hardened by design (RHBD) flip flop (FF) circuits are evaluated at the 7-nm and 5-nm bulk FinFET nodes. For a given RHBD technique, the 5-nm node design has a single-event upset (SEU) cross-section an order of magnitude higher than that at the 7-nm node. Such an increase in SEU cross-section was not seen with scaling of previous nodes. Simulations indicate that the increase in SEU cross-section is due to disproportionate changes in single-event transient pulse-widths and sensitive areas after an ion strike. A figure-of-merit is proposed to quantify the efficacy of a given RHBD technique. RHBD FF designs are evaluated using this metric to show the efficacy of spatial and temporal RHBD techniques at the 7-nm and 5-nm technology nodes at both nominal and reduced supply voltage operations.

(Digital Presentation) Efficient Mandrel Cleaning Process for Fin-FET Technology Node

In this work, the surface cleaning of amorphous silicon mandrel at Fin-FET technology node is demonstrated. The unclean mandrel surface can cause abnormal growth of the following ALDSIN spacer deposition which may transfer to protrusion or bridge defect at the final structures. We present several mandrel cleaning methods to study the quality of deposited ALDSIN and then put forward a model of abnormal growth of ALDSIN. Finally, it is demostrated that the protrusion or bridge defect can be obviously improved and avoid the yield loss by the optimization of the mandrel cleaning process.

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

SummaryThis paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.

Implementation of UART Design for RF Modules Using Different FPGA Technologies

This paper is focused on the designing of UART (Universal Asynchronous Receiver Transmitter) for RF based modules, which is a type of serial communication protocol, mainly used for short-distance, low speed and low-cost data transmission between two embedded systems or computer peripherals. These days RF-Microcontroller modules widely uses UART protocol for the interface with other hardware. A reduced FSM (Finite State Machine) UART design has been implemented on different FPGAs. The maximum achievable speed and their corresponding power consumption are calculated using these FPGAs. The proposed design is implemented using Verilog HDL and for simulation purpose, Xilinx ISE 12.1, 14.7, Xilinx Vivado 2018 and Intel Quartus Prime 19.1 are used. The smallest value of maximum power consumption i.e. 20.67mW at 105.47MHz frequency with 180nm technology node is achieved by Intel Max V among all the Intel and Xilinx devices. Furthermore, the maximum achievable frequency i. e. 769.48 Hz has been found in Virtex 4 FPGA device. Xilinx Virtex UltraScale+ devices occupy the minimum area which provides 16-nm FinFET Technology node.

Dummy Gate Footing Problems in Scaling Down of FinFET Structures

The use of sacrificial dummy gate has been a standard process for HKMG in planar CMOS and subsequent FinFET technologies. However, the scaling down of FinFET design has led to a significant increase for the aspect ratio of gate structure. The profile of the dummy gate is of great importance for device performance and control of the dummy gate footing has become a prominent challenge. Here we studied dummy gate footing during high aspect ratio gate etch and its influence on device performance using virtual fabrication methods. At 7/5 nm FinFET technology node (as defined in IRDS 2018), the channel capacitance of the HKMG, which contributes to the AC performance, is showing to have percentage level differences respect to the existence/absence of dummy gate footing. Other problems posed by the dummy gate footing for subsequent procedures are also discussed. Figure 1

SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies

Single-event (SE) performance of the guard-gate flip-flop (GG-FF) and conventional D-FF designs is evaluated at the 16- and 7-nm FinFET technology nodes. The heavy-ion test results show that at the 16-nm node, the GG-FF shows better SE performance for low-linear energy transfer (LET) particles and similar performance for high-LET particles compared with D-FF design. However, at the 7-nm node, the GG-FF shows better SE performance than the D-FF across a wide range of particle LET values. This behavior is due to the higher number of short SE transient (SET) pulses for high-LET particles at the 7-nm node. The heavy-ion test results are used to estimate the number of short SET pulses as a function of particle LET values.

On the Workload Dependence of Self-Heating in FinFET Circuits

Self-heating effect (SHE) is a major reliability concern in current and upcoming technology nodes due to its ability to increase the channel's temperature of transistor and leading to degradations in the key electrical characteristics such as carrier mobility. In this brief, we study SHE in a full processor at the 7nm FinFET technology node. This is the first work to analyze the impact that executed workloads on top of processors have on stimulating SHE. As matter of fact, SHE in transistors is driven by the workload-induced switching activities. When it comes to evaluating SHE, state of the art typically assumes that the switching frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sw</sub> and operating clock frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">clk</sub> of a circuit are the same, concluding that SHE is not a concern in digital circuits that operate in the GHz-range like processors. After analysis a wide range of workloads, our investigation revealed that the majority of transistors in the processor's netlist exhibit a switching frequency in the kHz-range even though the processor's clock is in the GHz-range. This is because that the majority of transistors are within the data paths and hence their switching is driven by the workload data and not by the clock itself. In addition, we also demonstrate for the first time the important role that the duty cycle (on-/off-ratio) induced by the running workload has on modeling SHE. All in all, the relatively low switching activities together with skewed duty cycles induce a wide variety in channel temperatures. Thus, highlighting the importance of considering the workload when studying SHE.

Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification

Mixed-signal machine learning (ML) classification has recently been demonstrated as an efficient alternative for classification with power expensive digital MOSFET circuits. In this paper, a topology based on independent double-gate (IDG) FinFET devices is proposed for classifying high-dimensional input data into multi-class output space with less power and area as compared with state-of-the-art MOSFET classifiers. To facilitate a high-resolution multiplication as a part of the classifier predictions, ML features and feature weights are, respectively, fed to the back and front gate inputs of the individual IDG-FinFET transistors. A classifier that considers the decisions of the individual predictors is designed at 30 nm FinFET technology node and operates at 333 MHZ with nominal supply voltage of one volt. To evaluate the performance of the classifier, a reduced MNIST dataset is generated. The original resolution is reduced from $28 \times 28$ features to $9 \times 9$ features and the most important features are selected with sequential backward selection algorithm. The system is simulated in SPICE, exhibiting prediction accuracy of 90%, energy consumption of 25 pJ per classification (over four times lower than similar state-of-the-art classifiers), area of 1,365 ${\mu }\text {m}^{2}$ , and a stable response under a wide range of system variations.

Precise Control of Poly-Silicon Height by Plasma Etching in FinFET Technology Node

The FinFET technology was brought to mass production for several years to replace the planar transistor structures. Critical process control is highly required for better device and yield performance.[1] When IC scale shrinks, the device performance becomes more and more sensitive to its physical dimension, in which the gate height is included. In the HKMG era, the metal gate height control can be traced back to the poly-silicon height control, including the wafer-level uniformity, wafer to wafer, and lot to lot. Our work is focused on the poly-silicon height control with plasma etch process. The gate height uniformity control was already reported in 2017 by inductively coupled plasma (ICP) etching process.[2] In this report, a precise control method from the point view of local height variation within die, surface induced polish process stability and advanced process control of the poly height planarization is discussed by plasma etching process. With an insertion of cap layer, the local poly-silicon height variation can be improved over 40%. A plasma treatment post the cap layer etch-back can reduce the break-through time of poly-silicon process, and thus improve the stability of CMP process as well as the CMP uniformity. An advanced process control of poly-silicon etch back process is implemented. Dynamic process time is dependent on the poly-silicon height post CMP process, which is due to the normal process variation, and 1% of the poly-silicon height variation after poly-silicon etch back is finally realized. This work was partially sponsored by Shanghai Rising-Star Program (B type). The authors would like to thank Tongxun Guo from Lam research for the support of constructive discussion. Reference: [1] C. Auth et al., “A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors,” in VLSI Symp. Tech. Dig., pp. 131–132, 2012. [2] Y. Wang et al., “Poly-Si Planarization by ICP Plasma Etch at FinFET Technology”, ECS Trans. 77(3), 71-76, 2017.

Precise Control of Poly-Silicon Height by Plasma Etching in FinFET Technology Node

In this paper, a holistic methodology for the dummy poly silicon height control is discussed, including within shot, within wafer, and wafer to wafer in IC mass production. With a certain process and integration control, the poly-silicon height can be precisely controlled, which is beneficial to the final metal gate height. The poly-silicon height can achieve a less than 2% variation within wafer. The variation of device and yield performance is hence much improved.

Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects

We model the temperature-dependent gate-induced drain leakage (GIDL) in FinFETs. Berkeley short-channel IGFET model-common multi gate (BSIM-CMG) model for FinFET uses the only band-to-band tunneling (BTBT) to model the GIDL mechanism, which is not sufficient to capture the GIDL at low electric field. The proposed model captures trap-assisted tunneling (TAT) at low electric field and BTBT at a high electric field, in the gate–drain overlap region. It contains a single piece expression for trap-assisted tunneling GIDL current, especially present in the sub-20-nm FinFET technology node. The model is validated with the measurement data and it accurately captures the physical behavior of GIDL current. The developed model can be implemented in industry standard compact models.

Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage

At the 14-/16-nm FinFET technology node, experimental heavy-ion single-event upset (SEU) cross sections have been obtained for a D flip-flop (DFF) with variation in supply voltage over a wide range of particle linear energy transfer (LET). An empirical model for predicting the SEU cross section as a function of supply voltage based on experimental data has been developed and verified. The results are consistent with low-LET particle irradiation findings from previous works that have indicated a strong exponential increase in SEU cross section with supply voltage scaling for FinFET technologies. Furthermore, this paper reveals the impact of supply voltage variations on a sensitive area for high-LET particle irradiation. The increase in cross section from nominal (0.8 V) to a specific reduced supply voltage for high-LET particle irradiation is constant and has been observed through experimental results across the high-LET particle spectrum. The 3-D TCAD simulations are used to characterize sensitive area affecting high-LET supply voltage-dependent SEU cross sections in the FinFET technology. The developed model will allow circuit designers to predict changes in the SEU cross section due to supply voltage variation for the 14-/16-nm technology node without extensive testing.

Exploiting SEU Data Analysis to Extract Fast SET Pulses

A method is presented to enhance single-event transient (SET) measurements by overcoming a common experimental limitation of minimum measurable pulse widths. As technology scales, SETs decrease in width and measurement circuits fundamentally cannot capture every fast transient capable of causing an error. A method has been developed to overcome this limitation by using a latch as a feedback-assisted fast transient capture circuit. Single-event upset (SEU) data are combined with SET data to extend pulsewidth acuity such that pulses faster than the minimum measurable SET pulsewidth are extracted. The method has been applied for a 14-/16-nm bulk FinFET technology node and predictions for logic single-event cross section reveal the impact of fast transients on the radiation response of logic circuits. Results including the extracted fast transients represent upper bound SEU cross sections. For high linear energy transfer (LET) particle irradiation, accounting for fast transients using the developed method results in negligible variation in logic SE cross section. However, for low LET particle irradiation, the method results in an order of magnitude increase in logic SE cross section.

Analysis of FinFET-Based Adiabatic Circuits for the Design of Arithmetic Structures

This paper presents the adiabatic logic called 2[Formula: see text]–[Formula: see text]–2[Formula: see text], which can operate with less number of transistors and high energy efficiency than the existing circuit styles. It is a dual rail logic operated by four-phase power clock (PC). The 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic is capable of operating through a wide range of frequency from 100[Formula: see text]MHz to 1[Formula: see text]GHz. Relentless scaling of MOSFETs towards lower technology nodes results in short channel effects in addition to increasing higher leakage current issues. In this scenario, FinFET advantageously replaces MOSFET with its unique features of the elimination of the short channel effects encountered by the MOSFETs with its gate structure that wraps around the channel completely. It incurs that the lower energy consumption and the feasibility of designing energy recovery circuits using FinFETs are analyzed in this paper. Comparatively, the energy efficiency of FinFET-based 2[Formula: see text]–[Formula: see text]–2[Formula: see text] against the [Formula: see text] and Positive Feedback Adiabatic Logic (PFAL) are analyzed. Simulation results also validate the robustness and efficiency of 2[Formula: see text]–[Formula: see text]–2[Formula: see text] adiabatic logic circuit under process parameter variations of FinFET technology. Complex adiabatic adders and multipliers taken as bench mark circuits have been designed using 32-nm FinFET technology node and the results validate the enhanced energy efficiency characteristics of 2[Formula: see text]–[Formula: see text]2[Formula: see text] over [Formula: see text] and PFAL designs.

Caution: Abnormal Variability Due to Terrestrial Cosmic Rays in Scaled-Down FinFETs

The variability due to the displacement damage defect is investigated for various bulk FinFET technology nodes. A random displacement damage from point to clustered defects is introduced by natural terrestrial radiation in arbitrary locations in the silicon channel region. Energy level, position, and size of the defect clusters are considered as variables, and the impact on device performance is investigated for various technology nodes with the aid of the TCAD simulation. It is found that even a displacement defect can cause significant device degradation as the technology node scales down beyond the 10-nm node. Particularly, the abnormal variability may become an issue at sub-6-nm node due to a limited volume of the fin width and the comparable size of the cluster defect.

Evaluation of variability using Schmitt trigger on full adders layout

The aggressive technology and voltage scaling which modern digital circuits are facing introduce a higher influence in metrics, as performance and power consumption, due to process variability. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7 nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 64.74% and 66.6% improvement in average delay and energy variability robustness, respectively.

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance

Negative capacitance field-effect transistor (NCFET) addresses one of the key fundamental limits in technology scaling, akin to the non-scalable Boltzmann factor, by offering a sub-threshold swing below 60 mV/decade. In this paper, we investigate how the NCFET technology can open the doors not only for the continuation of Moore’s law, which is approaching its end, but also for reviving Dennard’s scaling, which stopped more than a decade ago. We study NCFET for the 7-nm FinFET technology node, from physics to processors and demonstrate that prior trends in processor design with respect to voltage and frequency can be revived with the NCFET technology. Our work focuses on answering the following three questions towards drawing the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors: 1) to operate at higher frequencies without increasing voltage; 2) to operate at higher frequencies without increasing power density, which is substantial, because maintaining on-chip power densities under tight constraints due to limited cooling capabilities is inevitable; and 3) to operate at lower voltages, while still fulfilling performance requirements, which is substantial for the emerging Internet of Things, in which available power budgets for such devices are typically very restricted.

(Invited) FinFET Technology

This paper provides an overview of FinFET technology, including its unique advantages and challenges in device design and fabrication. Common myths on FinFET are clarified. A methodology to decipher the confusing FinFET technology node names is shared. Potential solutions to further scaling FinFET are discussed. The comparison between FinFET and other existing and emerging devices and materials is performed from manufacturing perspectives.

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node

Monolithic 3-D (M3D) IC is one of the potential technologies to break through the challenges of continued circuit power and performance scaling. In this paper, for the first time, we demonstrate the power benefits of M3D and present design guideline in a 7-nm FinFET technology node. The predictive 7-nm process design kit (PDK) and the standard cell library using both high-performance (HP) and low-standby-power (LSTP) device technologies are developed based on NanGate 45-nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. We implement full-chip M3D designs utilizing industry-standard physical design tools, and gauge the impact of M3D technology on performance, power, and area metrics. We also provide the design guidelines as well as a new partitioning methodology to improve M3D design quality. This paper shows that M3D designs outperform 2-D counterparts by 16% and 16.5% on average in terms of isoperformance total power reduction with 7-nm HP and LSTP cell library, respectively. This demonstrates the power benefits of M3D technology in both HP and low-power future generation devices.

Interaction of work function tuning and negative bias temperature instability for future nodes

Next generation finfet technology nodes will increasingly rely on the effective workfunction tuning to achieve the desired transistor VT as finfet doping is increasingly ineffective as a mean to tune VT. This work deals with metal gate workfunction engineering impact on bias temperature instability toward VT control in future nodes and its correlation with gate stack parameters. This work is divided in two parts. In the first part, the EWF extraction technique and its link to actual VT is investigated using a unique combination of CV/IV techniques. Using controlled experiments, a 400meV EWF modulation modulates NBTI significantly. The impact of bulk defects due to this modulation is also discussed.