Fin-type Field-effect Transistors Research Articles

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

In this study, a bulk fin-type FET (FinFET)-based capacitorless one-transistor dynamic random-access memory (1T-DRAM) was proposed. The fabrication process of the proposed 1T-DRAM was similar to that of a typical junctionless bulk FinFETs, except that the p-type doped body fin region operated as a charge storage region. The effects of the geometrical variations, such as the fin angle (θ fin) variation and line edge roughness (LER), which are inevitable in fabrication, on the transfer characteristics and memory performance of the proposed 1T-DRAM were studied. θ fin was varied from 90° to 80°, and 200 samples with the LER were analyzed. Results revealed that the transfer characteristics and memory performance were affected by geometrical variations. However, the proposed 1T-DRAM exhibited an excellent retention time in all cases because the charge storage region was separated from the region of operation.

Low power based ternary half adder using fin type field effect transistor technology

Low power based ternary half adder using fin type field effect transistor technology

Interactive Lattice and Process-Stress Responses in the Sub-7 nm Germanium-Based Three-Dimensional Transistor Architecture of FinFET and Nanowire GAAFET

The comprehensive layout-dependence lattice and process-stress variations and induced mobility gain in sub-7 nm germanium (Ge)-based Fin-type field-effect transistors (FinFETs) and gate-all-around (GAA) nanowire (NW)-type FETs are investigated through process-oriented stress simulation with lattice generated from strain-relaxed buffer (SRB) and source-drain (S-D) region. Analysis results reveal that the local lattice stressors mentioned above are the dominant stress resources in sub-7 nm FinFET and GAA transistor architectures. For FinFET architecture, the mobility performance is highly linearly proportional to the S-D length, and 49.01% and 105.96% gains are observed when S-D lengths of 5 and 50 nm are designed, respectively. To achieve simultaneous maximum integration density and effective performance enhancement of the three-dimensional transistor of concern, the design roles of narrow stacked pitch and channel length are explored. The maximum mobility enhancements are determined to be 231.89% and 288.90% for the Ge n- and p-type GAAFET analyzed herein, respectively.

Effective work function of TiN films: Profound surface effect and controllable aging process

Titanium nitride (TiN), with its tunable work function, serves as an electrode metal in the scaling fin-type field-effect transistor and plays the key role for low threshold operation. Measuring the effective work function of thin TiN films is desirable for rapid evaluation before device fabrication. In this work, Kelvin probe force microscopy is applied to study the impact of various factors on the surface potential of TiN films with an uncertainty below 30 mV. By scraping and gauging the potential evolvement of TiN in different circumstances, it is revealed that the surface effect is the major obstacle to determine the work function of the as-deposited TiN. For thick films, the potential drops over 530 mV for a fresh TiN surface relative to that of an aged one. For TiN films thinner than 5 nm, the potential changes by 290 mV due to surface oxidation. This enables a quantitative assessment on the effective work function as well as the surface charge density of TiN films.

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Multiple three-dimensional bottleneck barrier heights regarding fluctuated threshold voltage by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors

We study numerically on multiple three-dimensional bottleneck barrier heights (BBHs3D) which might be origins of the fluctuated threshold voltage (V th) induced by random dopant fluctuation, depending on a drain voltage (V d). It is confirmed from variance inflation factor that multiple regression analysis with all the BBHs3D is not suitable to investigate the fluctuated V th. Since 3D bottleneck barrier height minimum (BBH3D,min) has a very high correlation with the other BBHs3D, simple regression analysis with even only one BBH3D,min has a very high correlation with the V th. There is an optimal ordinal number for multiple BBHs3D to be considered to investigate the fluctuated V th. It has been demonstrated that the V th can be expressed more accurately by using my proposed method of simple regression analysis considering optimal multiple BBHs3D. Although the optimal multiple BBHs3D decreases when the V d increases, the improvement is relatively similar regardless of the V d.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.

Universal Filter Design Using 45 nm FinFET Technology-Based Floating Current Source

ABSTRACT Fin type Field Effect Transistor (FinFET) technology is a promising technology for single-digit nanometric dimensions. FinFETs are used to increase the performance by reducing the power consumption as the two gate voltages are controlled dependent and/or independently. This work explores the design of a Floating Current Source (FCS) using Double Gate (DG) FinFET and its application of a universal filter. The designed FinFET based FCS operates at 0.15 V power supply, the power consumption of the circuit is 51nW and bandwidth is approximately 100 MHz. The proposed FCS based filter circuit is simulated in LTspice with the FinFET 45 nm PTM-MG model. The filter topology behavior has been tested with an experimental study using the LM13700 integrated circuit and the experimental results are demonstrated. The proposed FinFET based circuit and its application can be used for the design of systems that require low power consumption and low chip area.

Performance Evaluation of Negative-Capacitance Fin-Type Field Effect Transistor-Based Static Random-Access Memory with Mixed-Mode Simulation

Electrical characteristics of fin-type field-effect transistor with negative capacitance effect (NCFinFET) are investigated coupled with the Landau-Khalatnikov equation for ferroelectric materials in this study. Moreover, Technology Computer Aided Design (TCAD) mixed-mode simulation is carried out to evaluate and compare the performance of NCFinFET-based static random access memory cell (NC-SRAM) with a traditional FinFETbased SRAM one. It is shown NC-SRAM has higher static noise margin (SNM) and better anti-interference capability than conventional SRAM with the same supply voltage. The static read, hold, and write noise margins (RSNM, HSNM, and WSNM, respectively) for NC-SRAM increased by 10%, 30%, and 15%, respectively, and the access disturb stability improved by 80%. Simulation results also reveal that the read stability increases with increasing ferroelectric layer thickness, while the write stability exhibits a non-monotonic trend with ferroelectric layer thickness for NC-SRAM.

Dependence of three-dimensional bottleneck barrier height minimum on threshold voltage fluctuated by ion implantation of source and drain extensions in silicon-on-insulator triple-gate fin-type field-effect transistors

We have investigated the threshold voltage (Vth) fluctuated by ion implantation (I/I) of the source and drain extensions for a leading-edge variability-tolerant device structure using a three-dimensional (3D) process and device simulations. We have previously reported that the fluctuated Vth is characterized by the variation of the minimum value of the 3D bottleneck barrier height (BBH3D,min) of electrostatic potential from the source contact to the corresponding bottleneck points in the entire device. Standardized multiple regression analysis indicated that the 3D position where BBH3D,min exists (BBP3D,min) has only a weak correlation with the Vth. The effect of the BBP3D,min on the Vth is not significantly large; therefore, the Vth can almost be explained by only the value of BBH3D,min over the entire Vth region, despite the drain bias condition.

Relative Study of Analog Performance, Linearity, and Harmonic Distortion Between Junctionless and Conventional SOI FinFETs at Elevated Temperatures

This paper reports a comparative study of the analog performance, linearity and harmonic distortion characteristics between junctionless (JL) and conventional silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) at elevated temperatures (300–500 K). A numerical device simulator is used for this study. Analog performance parameters of a JL FinFET are found to be less sensitive to variation in temperature as compared with its IM counterpart. Linearity is also found to be better for JL devices than IM devices for the entire temperature range. Moreover, harmonic distortion is found to be less for JL devices than IM devices.

Design and analysis of INDEP FinFET SRAM cell at 7‐nm technology

AbstractThe reduction in size of metal oxide semiconductor (MOS) devices results in increase in leakage power dissipation, which occurs due to the short‐channel effects in subthreshold region. Now a day's power dissipation is one of the crucial issues that the modern electronic industry is facing. Fin‐type field‐effect transistor (FinFET) can be proven as a best substitute to reduce leakage power dissipation in logic circuits. Degradation of performance with process variations is of major concern and needs to design FinFET circuits with minimum leakage power dissipation. In this paper, static random‐access memory (SRAM) cell is designed using low power shorted‐gate (SG) FinFETs at 7‐nm technology to minimize leakage power dissipation besides improving other performance parameters like static noise margins (SNMs) and power delay product (PDP) as well. The various parameters are analyzed using butterfly and N‐curve methods. The ASAP7 PDK is used to design SRAM cells using Cadence Virtuoso tool. The simulated results show that FinFET input‐dependent (INDEP) technique reduces the leakage power dissipation by 32.08% and 13.50%, respectively, in read and write conditions of FinFET SRAM cell. The Monte‐Carlo simulation results show the reduction in average power using INDEP approach at ±10% process, voltage and temperature (PVT) variations under 3σ Gaussian distribution of FinFET SRAM cell.

Three-dimensional exploration of the origin of threshold voltage fluctuation of silicon-on-insulator triple-gate fin-type field-effect transistors caused by ion implantation to source and drain extensions

The origin of the Vth fluctuation induced by ion implantation (I/I) into the source and drain extensions (SDEs) of triple-gate (tri-gate) fin-type field-effect transistors has been three-dimensionally explored by both three-dimensional (3D) process and device simulations. The 3D electrostatic potential distributions in the whole Si channel fin are analyzed, and it is confirmed that the 3D electrostatic potential distribution of the lowest Vth sample is more undulated than that of the highest Vth sample due to implanted arsenic (As+) ions to the SDEs irrespective of the drain bias condition. We found also that the minimum of bottleneck barrier heights (BBHs) in the Si whole channel fin, which is called BBH3D,min, is strongly correlated with the Vth, and therefore is a strong indicator to study the Vth of the device. It now became obvious that the origin of the SDE I/I-induced Vth fluctuation is a variation of BBH3D,min in the whole channel for the first time. The obtained results are beneficial for the research and development of such future devices.

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits

In this paper, we report on the efforts of applying the dynamic-adjusting threshold-voltage scheme (DATS) to the design of an independent-gate (IG)-mode fin-type field-effect transistor (FinFET) circuit. DATS makes use of the intrinsic advantage of the IG-mode FinFET to adjust the threshold of the front gate with the back-gate bias adaptively according to the operating frequency. Consequently, the power consumption, especially leakage power of the circuit, would be reduced effectively without circuit performance deterioration. By further comparing the circuits where the DATS scheme is employed with the circuits that do not adopt the scheme, the power optimization levels with different path delays in different operating frequency ranges are discussed in detail. A design instance of DATS based on digitally controlled phase-locked loop is implemented with an ASAP 7-nm FinFET model. Simulation results illustrate that by employing DATS the power reduction could be up to 30% in the best case.

Origin of threshold voltage fluctuation caused by ion implantation to source and drain extensions of silicon-on-insulator triple-gate fin-type field-effect transistors using three-dimensional process and device simulations

The threshold voltage (Vth) fluctuation induced by ion implantation (I/I) in the source and drain extensions (SDEs) of a silicon-on-insulator (SOI) triple-gate (Tri-Gate) fin-type field-effect transistor (FinFET) was analyzed by both three-dimensional (3D) process and device simulations collaboratively. The origin of the Vth fluctuation induced by the SDE I/I is basically a variation of a bottleneck barrier height (BBH) due to implanted arsenic (As+) ions. In particular, a very low and broad Vth distribution in the saturation region is due to percolative conduction in addition to the BBH variation. Moreover, it is surprisingly found that the Vth fluctuation is mostly characterized by the BBH of only a top surface center line of a Si fin of the device. Our collaborative approach by 3D process and device simulations is dispensable for the accurate investigation of variability-tolerant devices. The obtained results are beneficial for the research and development of such future devices.

Analysis of In-Line Process Parameters of the Unity Gain Frequency of HKMG Bulk FinFET Devices

This research explores the electrical characteristics of the unity gain frequency ( ${F}_{t}$ ) in relation to the experimental in-line process parameters of 16-nm high- $\kappa $ metal gate bulk fin-type field effect transistor devices. Because ${F}_{t}$ is dependent on the transconductance ( ${G}_{m}$ ) and effective gate capacitance ( ${C}_{\textsf {gg}}$ ), a sensitivity analysis of these two factors is applied to determine key in-line process parameters. The engineering results of this letter indicate that ${G}_{m}$ and ${C}_{\textsf {gg}}$ are significantly fluctuated by six in-line process parameters, including the gate length, fin height, high- $\kappa $ /interfacial layer thickness, source/drain (S/D) proximity, S/D depth, and gate height. These six parameters fluctuate ${F}_{t}$ at the same time, with ${G}_{m}$ as the dominant factor.

Influence of hydrogen in silicon nitride films on the surface reactions during hydrofluorocarbon plasma etching

The influence of the amount of hydrogen (H) in hydrogenated silicon nitride films (SixNy:Hz) on the etching properties and etching mechanism are unclear for hydrofluorocarbon plasma etching. Therefore, the authors have investigated the effect of H in SixNy:Hz films on the surface reactions during CH2F2/Ar/O2 plasma etching by experimental and numerical simulation techniques. The experimental etch yield (EY) and polymer layer thickness (TC−F) values for SixNy:Hz films with different H concentrations of 2.6% (low-SiN), 16.8% (mod-SiN), and 21.9% (high-SiN) show different trends with the CH2F2/(CH2F2 + O2) flow rate ratio. To understand the mechanism of the different etching properties, the authors estimated the chemical reaction probabilities of the H outflux between F, O, N, C, and Si dangling bonds using first principles calculations and the results of Fourier transform infrared spectroscopy. Based on the estimated reaction probabilities, the authors modeled the surface reactions of SixNy:Hz films under the assumption that the H outflux mainly scavenges incident F radicals (the main etchant species). The authors also consider that the reaction between H and N from outfluxes decreases the desorption reactions of C2N2 and HCN, resulting in a larger TC−F value. Comparing the simulation results of the trends in the whole flow rate ratio range and the absolute values of EY and TC−F with experimental data, the surface model can successfully explain the mechanism. Furthermore, the authors demonstrated time-dependent etched profile and damage distribution for fin-type field-effect transistor SixNy:Hz side-wall etching using the three-dimensional voxel-slab model with the above surface reactions to obtain knowledge about the effect of H on the etched profile and damage distribution. The results show that the etched profile and damage distribution on the Si fin structure are very different for low-SiN and high-SiN because of the different EY and TC−F values induced by different H outfluxes. These results indicate that it is important to carefully control both the etching process and amount of H in the SixNy:Hz film to achieve high-performance advanced complementary metal oxide semiconductor devices.

Very low and broad threshold voltage fluctuation caused by ion implantation to silicon-on-insulator triple-gate fin-type field effect transistor using three-dimensional process and device simulations

The threshold voltage (Vth) fluctuation induced by the ion implantation to the source and drain extensions (SDE) of a silicon-on-insulator (SOI) triple-gate (tri-gate) fin-type field-effect transistor (FinFET) was analyzed for the first time with the use of realistic positional information of discretely doped ions by both three-dimensional (3D) process and device simulations. Interestingly, it was found that the Vth fluctuation induced by SDE ion implantation has a very low and broad distribution on the low-Vth side even in the case of a robust device structure such as SOI tri-gate FinFET. Furthermore, for the first time, it was quantitatively demonstrated using a proposed cluster percolation model that the origin of the very low and broad Vth fluctuation is the conductive percolation among unintentionally doped ions in the channel region of the device. These results would contribute to the realization of robust transistors.

Process Variation Analysis and Optimization of a FinFET-Based VCO

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS for nanoscale technologies. In this paper, the viability of a mixed-signal design for FinFET-based technologies using a nanoscale current-starved voltage controlled oscillator (VCO) is investigated. Design issues are analyzed and a comparison between a CMOS VCO and a FinFET-based VCO is presented. The figures-of-merit used for comparison are center frequency and frequency–voltage ( ${f}$ – ${V}$ ) characteristics under process variation. Models are developed for the ${f}$ – ${V}$ characteristics of both the CMOS and FinFET VCOs. In addition, width quantization-aware modeling has been performed for the FinFET-based VCO using a polynomial metamodel, which can be used for further optimization. The quantization aware modeling is highly accurate as evident from a correlation coefficient ${R^{2}}$ of 0.999 and root mean square error of 6.2 MHz. The FinFET VCO has $5.5 {\times }$ faster oscillation frequency with 2.6% variability as opposed to 19.7% for the CMOS VCO. To the best of the authors’ knowledge, this is the first paper that examines FinFET technology with respect to process variation in mixed signal designs at the circuit level, and presents a quantitative as well as qualitative comparison between CMOS and FinFET technologies.

Reliability evaluation of high-performance, low-power FinFET standard cells based on mixed RBB/FBB technique**Project supported by the National Natural Science Foundation of China (No. 61306040), the State Key Development Program for Basic Research of China (No. 2015CB057201), the Beijing Natural Science Foundation (No. 4152020), and Natural Science Foundation of Guangdong Province, China (No. 2015A030313147).

With shrinking transistor feature size, the fin-type field-effect transistor (FinFET) has become the most promising option in low-power circuit design due to its superior capability to suppress leakage. To support the VLSI digital system flow based on logic synthesis, we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell. This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis. The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell. For comparison, a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated. Experimental results show that the optimized cells achieve standard deviation reduction of 39.1% and 30.7% at most in worst-case delay and input-dependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage can be up to 98.37% and 24.13%, respectively, which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.