Interactive Lattice and Process-Stress Responses in the Sub-7 nm Germanium-Based Three-Dimensional Transistor Architecture of FinFET and Nanowire GAAFET

Abstract

The comprehensive layout-dependence lattice and process-stress variations and induced mobility gain in sub-7 nm germanium (Ge)-based Fin-type field-effect transistors (FinFETs) and gate-all-around (GAA) nanowire (NW)-type FETs are investigated through process-oriented stress simulation with lattice generated from strain-relaxed buffer (SRB) and source-drain (S-D) region. Analysis results reveal that the local lattice stressors mentioned above are the dominant stress resources in sub-7 nm FinFET and GAA transistor architectures. For FinFET architecture, the mobility performance is highly linearly proportional to the S-D length, and 49.01% and 105.96% gains are observed when S-D lengths of 5 and 50 nm are designed, respectively. To achieve simultaneous maximum integration density and effective performance enhancement of the three-dimensional transistor of concern, the design roles of narrow stacked pitch and channel length are explored. The maximum mobility enhancements are determined to be 231.89% and 288.90% for the Ge n- and p-type GAAFET analyzed herein, respectively.