An analytical threshold voltage model for nanoscale GAA MOSFETs including effects of hot-carrier induced interface charges

Abstract

As the channel length rapidly shrinks down to the nanoscale regime, a Gate All Around (GAA) MOSFET structure has been considered as a potential candidate for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we present an analytical model including the hot-carrier induced interface charge effect for undoped GAA MOSFETs. We have studied the hot-carrier degradation effects on the surface potential and the threshold voltage of nanoscale GAA MOSFETs. Basing on this new device model, we found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Our obtained results showed that the analytical model is in close agreement with the 2-D numerical simulation over a wide range of device parameters. The proposed analytical approach may provide a theoretical basis and physical insights for GAA MOSFET design including the hot-carrier degradation effects.