Abstract
Increased device degradation due to hot-carrier effects in nanoscale double-gate (DG) MOSFETs is investigated. We have studied the hot-carrier degradation effects on surface potential, threshold voltage and drain-induced barrier lowering (DIBL) of nanoscale DG MOSFETs. Exploiting this new device model, we have found that the degradation becomes worse when the channel length gets shorter and the minimum potential's position is affected by the hot-carrier induced localised interface charge density. DIBL effect is more pronounced in very short channel lengths (L less than 40 nm) in the presence of the hot-carrier effects. The results showed that the analytical model is in close agreement with the 2-D numerical simulation over a wide range of device parameters.
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