Fin Field Effect Transistor Devices Research Articles

Machine-learning-assisted rational design of 2D doped tellurene for fin field-effect transistor devices

Fin field-effect transistors (FinFETs) have been widely used in electronic devices on account of their excellent performance, but this new type of device is facing many challenges because of size constraints. Two-dimensional (2D) materials with a layer structure can meet the required thickness of FinFETs and provide ideal carrier transport performance. In this work, we used 2D tellurene as the parent material and modified it with doping techniques to improve electronic device performance. High-performance FinFET devices were prepared with 23 systems screened from 385 doping systems by a combination of first-principle calculations and a machine-learning (ML) model. Moreover, theoretical calculations demonstrated that 1S1@Te and 2S2@Te have high carrier mobility and stability with an electron mobility and a hole mobility of 6.211×104 cm2 V-1 S-1 and 1.349×104 cm2 V-1 S-1, respectively. This work can provide a reference for subsequent experiments and advance the development of functional materials by using an ML-assisted design paradigm.

A review on effect of various high-k dielectric materials on the performance of FinFET device

The scalability of bulk CMOS faced various possible issues due to inherent material and process innovation constraints. Alternatively, transistor devices with supplementary gates, such as the Fin Field-effect transistor (FinFET) structure has attracted developing interest during the last few generations of their emergence, attributable to the appropriate control of the gate electrode over subthreshold parameters and seem to be favorable for Ultra large-scale integration, resulting in excessive immune function to short-channel effects (SCEs). In this paper, we will see the effect of several types of high-k gate dielectrics materials i.e Hafnium oxide (HfO2), Lanthanum doped zirconium oxide (LaZrO2), Silicon dioxide (SiO2), crystalline-silicon (c-Si), and polycrystalline-silicon (poly-Si), etc. channels are characterized for the short channel effects (SCEs), leakage current, Ion/Ioff ratio, drain induced barrier lowering (DIBL), and subthreshold swing (SS). The effect of important device parameters is considered regarding SCEs. The variation of the materials indicates improvements for the SCEs in FinFETs device architecture and also enhanced effective carrier mobility. Hence, we can clearly see that the use of high-k gate material has allowed for effective control of the diminishing of short channel effects.

Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application

The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier

The major motivation behind transistor scaling is the requirement for high-speed transistors with lower fabrication costs. When the fin thickness or breadth is smaller than 10 nm in a trigate FET, charges travel in a nonconfined fashion, resulting in the creation of energy subbands and causing volume inversion. In comparison to the carrier near a surface inversion layer, volume inversion experiences less interface scattering. In large-scale integrations, we have focused on developing a 3D model for surface potential by establishing the three-dimensional Poison’s equation and building a unique fin field-effect transistor (FinFET) structure. In this context, there is a growing interest in developing a low-cost, simple solution that combines plastic (polymer) as a substrate and organic materials to create electronics such as monitors and sensors. The research examines characteristics such as silicon width, oxide thickness, doping concentration, metal work-function about gate, and various surface potentials. For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. This work is aimed at improving the semiconductor design structure by adjusting device parameters, analyzing the results, establishing the best FinFET device preferences, and selecting an application for the optimized device. The 3D Poisson’s equation may be used to create an analytical model of a trigate nanosize FinFET, which can then be tested using a TCAD simulator. By constructing such a FinFET, we can structure and analyze various electrostatic parameters. To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. The infrastructure’s support denotes a computationally advantageous numerical model that accurately depicts a FinFET. The work presents a compact model for semiconductor manufacturing that permits separate IC productions while achieving higher levels of excellence and using less power. The design outperforms the CMOS by 22.7% in gain, 31.48% in power consumption, and 12.72% in CMRR, while operating at a 5 GHz unity gain frequency.

Two-dimensional dopant potential mapping in a fin field effect transistor by off-axis electron holography

Progress in the development of nanometer scaled Fin Field Effect Transistor (FinFET) devices is affected by a lack of understanding of relevant dopant diffusion phenomena due to limited experimental data. In particular, 2D dopant potential mapping by electron holography in 3D FinFET devices has been challenged by the overlap of electrically active fins, metal films, and dielectric films in the electron beam direction. This paper presents methodology on how to map dopant potential in modern FinFET devices. A custom-device structure was developed, which preserved all essential features of the device manufacturing process. The dopant reconstruction method is suggested to account for the presence of materials other than silicon fin between fins. A comparison of lateral dopant potential profiles with device simulations offers agreement within 0.32 V. Compositional non-uniformity of materials between fin devices is identified as the main limiting factor. A further reduction of compositional non-uniformity should allow for quantitative 2D dopant potential mapping with high sensitivity to probe the effects of dopant segregation, deactivation, and diffusion kinetics in 3D FinFET devices at the nanometer scale.

Automated calibration of model-driven reconstructions in atom probe tomography

Traditional reconstruction protocols in atom probe tomography frequently feature image distortions for multiphase materials, due to inaccurate geometric assumptions regarding specimen evolution. In this work, the authors’ outline a new reconstruction protocol capable of correcting for many of these distortions. This new method uses predictions from a previously developed physical model for specimen field evaporation. The application of this new model-driven approach to both an experimental semiconductor multilayer system and a fin field-effect transistor device (finFET) is considered. In both systems, a significant reduction in multiphase image distortions when using this new algorithm is clearly demonstrated. By being able to quantitatively compare model predictions with experiment, such a method could also be applied to testing and validating new developments in field evaporation theory.

Single β-Ga2O3 nanowire based lateral FinFET on Si

A fin field-effect transistor (FinFET) based on single β-Ga2O3 nanowire with a diameter of ∼60 nm transferred to Si substrate is demonstrated. The FinFET device shows good saturation performance within a drain-to-source voltage up to 5 V and exhibits a high on/off ratio of ∼4 × 108, a system-limit low leakage current (∼4 fA), and a relatively low subthreshold swing (∼110 mV). Simulation shows that the channel of the FinFET depletes much faster than that of the back-gate FET with negative gate bias, which is consistent with the measurement results. Moreover, trap-related 1/f noise and 1/f2 noise have been identified according to low frequency noise analysis, and a carrier number fluctuation is expected to be the dominant 1/f noise mechanism in the β-Ga2O3 FinFET in this work.

A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET

Several ultra-low power applications, that do not require high performance, can benefit from operation at the lowest possible supply voltage. Scaling of supply voltage is an effective method to reduce the energy consumption in digital circuits. The fundamental limit for supply voltage has been established as 36 mV for planar complementary metal oxide semiconductor (CMOS) circuits based on Shannon’s channel capacity theorem. Owing to its near ideal sub-threshold characteristics, fin field effect transistor (FinFET) devices are a better fit for ultra-low voltage applications than planar devices. In this work, the fundamental limit on supply voltage for FinFET based logic circuits has been established for the first time. This theoretical limit is found to be significantly lower than the limit for planar CMOS circuits. The effect of variation of temperature and device design parameters on this fundamental limit is also explored. The analysis is extended to other logic gates such as NAND gate. Since the operation of a FinFET device in the ultra-low voltage domain is quite different from its planar counterpart, a novel physics based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed for a FinFET device to calculate this fundamental limit. Such a current model is of great importance to a circuit designer because of the ease it offers for the back of the envelope calculations. The logic gates operating in this regime are then analyzed using this proposed model.

Integration of Si0.7Ge0.3 fin onto a bulk-Si substrate and its P-type FinFET device fabrication

In this study, the integration of a high-mobility Si0.7Ge0.3 fin onto a bulk-Si substrate utilizing a shallow trench isolation (STI) last strategy and its fin field effect transistor (FinFET) device fabrication are investigated. A high-quality Si0.7Ge0.3 fin was first achieved by developing a process of the epitaxial growth of Si0.7Ge0.3, the fin etching of both the Si substrate and the Si0.7Ge0.3, the low-temperature STI densification annealing and the SiN liner. Then, a Si0.7Ge0.3 channel FinFET device was successfully fabricated by employing a newly developed spacer etching process, the annealing of a low temperature source and drain activation, an in-situ O3 passivation process, and an Al2O3/HfO2 bi-layer gate dielectric. As a result, a drive current I on of 331 μA μm−1 under V DS = V GS = −0.8 V was obtained without any strain-induced mobility enhancement technology. Using this bulk FinFET-compatible process, a high I on/I off ratio of ∼5 × 105, an excellent subthreshold slope (SS) of 73 mV decade−1 and a drain induced barrier lowering of 20 mV V−1 were demonstrated. Its excellent SS performance indicates that a good interface quality of the Si0.7Ge0.3 fin is obtained after the fabrication of its FinFET device. The above results confirm that these newly developed processes can provide a potential solution for the integration of high-mobility channels onto a bulk Si substrate and its FinFET device fabrication.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{D}$ </tex-math></inline-formula> dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics.

In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.

GaN FinFETs and trigate devices for power and RF applications: review and perspective

Gallium nitride (GaN) is becoming a mainstream semiconductor for power and radio-frequency (RF) applications. While commercial GaN devices are increasingly being adopted in data centers, electric vehicles, consumer electronics, telecom and defense applications, their performance is still far from the intrinsic GaN limit. In the last few years, the fin field-effect transistor (FinFET) and trigate architectures have been leveraged to develop a new generation of GaN power and RF devices, which have continuously advanced the state-of-the-art in the area of microwave and power electronics. Very different from Si digital FinFET devices, GaN FinFETs have allowed for numerous structural innovations based on engineering the two-dimensional-electron gas or p–n junctions, in both lateral and vertical architectures. The superior gate controllability in these fin-based GaN devices has not only allowed higher current on/off ratio, steeper threshold swing, and suppression of short-channel effects, but also enhancement-mode operation, on-resistance reduction, current collapse alleviation, linearity improvement, higher operating frequency, and enhanced thermal management. Several GaN FinFET and trigate device technologies are close to commercialization. This review paper presents a global overview of the reported GaN FinFET and trigate device technologies for RF and power applications, as well as provides in-depth analyses correlating device design parameters to device performance space. The paper concludes with a summary of current challenges and exciting research opportunities in this very dynamic research field.

Quantitative evaluation of process-induced line-edge roughness in FinFET: Bayesian regression model

With the aggressive scaling down of the minimum feature size of advanced metal–oxide–semiconductor devices, it has become imperative to design and fabricate process-variation-immune devices. Technology computer-aided design simulations are typically used to test thousands of devices for process-variation immunity, but the process is computationally expensive. In this work, we propose a novel approach to simulate and predict the current–voltage characteristics of fin field-effect transistor devices with process-induced line-edge roughness (LER), within a few seconds. We exploit the Bayesian linear regression model to estimate the mean and standard deviation of the drain-to-source current (I DS) for an arbitrary gate voltage (V GS) and LER profile. We evaluate the prediction accuracy in terms of the mean absolute percentage error (MAPE) and root mean square error (RMSE). The MAPEs for the mean and standard deviation of I DS are <1% and <20%, respectively, and the corresponding RMSEs are 0.0804 and 0.0263, respectively. Once the I DS–V GS distribution is estimated by means of this novel approach, the distributions of other device metrics such as the threshold voltage and off-state leakage current can be estimated.

Leakage reduction technique for nano-scaled devices

PurposeThe purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology.Design/methodology/approachBecause of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices.FindingsThis study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology.Originality/valueAll the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node

A flexible framework is obtained for enhancing both the thermal and electrical performance of fin field-effect transistor (FinFET) technology. Investigation of the nanoscale heat conduction within a short-channel field-effect transistor can be regarded as an emerging challenge related to future-generation transistors. In this work, we report the electrothermal transport in a 10 nm silicon-on-insulator (SOI) FinFET based on the dual-phase-lag model and modified drift-diffusion motions. We found that electron mobility decreases along the channel due to carrier confinement under higher electric field. In addition, the surface detection temperature indicates that the self-heating process is localized between the source and drain region. As promising results, high-κ metal-oxide and lower thermal boundary resistance can optimize the nanoscale heat transport in the SOI FinFET device.

TCAD Simulation Study of Single-, Double-, and Triple-Material Gate Engineered Trigate FinFETs

A detailed comparative performance analysis of the Trigate Fin Field Effect Transistor (FinFET) device with different structures such as Single-Material Gate (SMG) FinFET, Double-Material Gate (DMG) FinFET, and Triple-Material Gate (TMG) FinFET has been done. Silvaco Atlas Technology Computer-Aided Design (TCAD) tool is used to model the Trigate FinFET device structures and to characterize all the electrical parameters of the device. The simulation results confirm that TMG FinFET device structure shows better performance than SMG and DMG FinFET device structures, in terms of device electrical parameters such as surface potential, electric field, and drain current. Moreover, TMG FinFET device structure exhibits an excellent transconductance of 0.28 μA/V when compared with SMG FinFET (0.21 μA/V) and DMG FinFET (0.24 μA/V).

Bias-Dependent Variation in FinFET SRAM

In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Drain-induced barrier lowering (DIBL) and the variation in DIBL are found to exhibit a logarithmic dependence with drain bias in the advanced node FinFET devices. Correctly capturing the DIBL and device variation as a function of drain bias is required, as the SRAM operation voltage range is expanded. We show the improved hardware correlation in Vmin yield and the improved slow corner read performance when the Vds-dependent variation is considered.

Effect of source-drain conduction in single-event transient on nanoscaled bulk fin field effect transistor

Fin field effect transistor (FinFET) is a most widely used structure when the field effect transistor is scaled down to 30 nm or less. And there are few studies on single-event transient of FinFET devices with gate length below 30 nm. The single-event-transient on FinFET with gate length below 30 nm is worth studying. The single-event-transient responses of bulk FinFETs with 30 nm, 40 nm, 60 nm and 100 nm gate length are examined by using the pulsed laser and technology computer-aided design (TCAD) simulation in this article. First, we use the pulsed laser to ionize the gate of the FinFET device and detect the transient drain current of the FinFET device. The experimental results show that there are obvious platforms for the transient drain current tails of FinFETs with different gate lengths, and the platform current increases as the gate length of FinFET becomes shorter. The charges collected in the platform of FinFET devices with gate lengths of 100, 60, 40, and 30 nm are 34%, 40%, 51%, and 65% of the total charge collected in transient drain current, respectively. Therefore, when the FinFET device with the gate length below 100 nm, the platform current will seriously affect the device performance. Second, we use TCAD to simulate the heavy ion single-event effect of FinFET device and study the generation mechanism of platform region in transient drain current. The TCAD simulation explains this mechanism. Laser or heavy ions ionize high concentration electron-hole pairs in the device. The holes are quickly collected and the high concentration electrons are left under the FinFET channel. High concentration electrons conduct source and drain, generating the source-to-drain current at the tail of the transient drain current. Moreover the source-drain conduction enhances the electrostatic potential below the FinFET channel and suppresses high-concentration electron diffusion, making source-to-drain current decrease slowly and form the platform. The transient drain current tail has a long duration and a large quantity of collected charges, which seriously affects FinFET performance. This is a problem that needs studying in the single-event effect of FinFET device. It is also a problem difficult to solve when the FinFET devices are applied to spacecraft. And the generation mechanism of the transient drain current plateau region of FinFET device can provide theoretical guidance for solving these problems.

Measurement of SiGe composition in 3-D semiconductor Fin Field Effect Transistor devices

A Transmission Electron Microscopy (TEM)-based method is suggested to measure the composition of SiGe in 3-D structures using Electron Energy Loss Spectroscopy (EELS). The method accounts for the presence of films other than SiGe within the TEM lamella in the electron beam direction. The partial cross section of inelastic scattering of Ge was calibrated using a reference structure, which was earlier analyzed by Electron Energy Dispersive X-ray Analysis (EDX) and Secondary Ion Mass Spectrometry. The composition of SiGe in the p-FET Fin Field Effect Transistor devices with the overlaying Si oxynitride films was measured as a demonstration of the method. We show that the application of EELS yields smaller measurement errors of the SiGe composition as compared to EDX. The effect of beam damage in thin SiGe films surrounded by Si oxynitride is evaluated and compared to the blanket Si/SiGe structures. The method can be applied to the development of novel devices and state-of-the-art processes where the composition of SiGe plays a critical role.