Fill Capability Research Articles

Simulation and Experimental Activity for the Evaluation of the Filling Capability in External Gear Pumps

Partial electrification of hydraulic circuits to achieve energy savings requires an increase in the angular speed of the positive displacement pumps, with the risk of incomplete filling. In this context, the paper focuses on developing a computational fluid dynamics (CFD) model using SimericsMP+ for two external gear pumps, namely helical and spur type gears. The objective of this study is the analysis of the phenomena occurring on the suction side under conditions of incomplete filling at high speeds. Both CFD models have been validated by conducting experimental tests for measuring the flow rate delivered at various inlet pressures and angular speeds. The experimental results confirm the model’s capability to accurately detect the operating conditions at which the delivered flow rate starts to decrease due to the partial filling of the inter-teeth chambers. Furthermore, this paper investigates the effects of certain geometrical modifications to the spur gear pump. Specifically, the influence of the gear’s width-to-diameter ratio is studied, revealing that a lower ratio leads to slightly better filling. Conversely, increasing the inlet port diameter results in no improvement. Based on this study, the modelling approach appears to be accurate enough to serve as design tool for optimizing pumps to improve their filling capability.

Optimized ECD Cu RDL Process with Via Filling Capability for Next Generation Packaging

Abstract Next generation mobile devices, especially those with 5G capability, will require higher functionality and speed in combination with shrinking component as well as package dimensions. These requirements pose challenges to upcoming heterogeneous integration. In order to account for the increasingly complex technologies, filling of vias with copper will be required for packaging of the various components. Examples for such via filling applications include next generation radio frequency (RF) filters and multilayer redistribution layers (RDLs). However, the size scales of these applications vary from 100 μm to sub 5 μm. In addition to via filling of different dimensions and aspect ratios, the copper electrodeposition process is also supposed to be able to plate lines and pads within the RDLs. A combination of electrochemical and spectroscopic experiments was applied to optimize organic plating additives with respect to their suitability to deposit copper into this broad variety of structures.

Simulation of the Filling Capability in Vane Pumps

In positive displacement pumps, the main volumetric loss at high speed is due to the incomplete filling of the variable volume chambers. The prediction of the limit speed and of the maximum flow rate delivered by a pump can be obtained only through Computational Fluid Dynamics (CFD) simulations, since the shape, the orientation, and the movement of the chambers with respect to the inlet volume must be considered, along with the non-uniform distribution of the gaseous phase, due to the dissolved air release. In this paper, the influence of different geometric parameters on the filling of a vane pump has been investigated through the commercial software PumpLinx®. At first, a model of a reference pump has been created and validated with different configurations of the suction flow area, then a simplified model has been used for assessing the influence of the geometry of the rotating assembly. It was found that a pump with a low ratio between the axial thickness and the diameter has a higher volumetric efficiency if the chambers are fed from one side only. Opposite behaviors were found in the case of pumps with small diameters and high thicknesses. Moreover, the filling could be improved by increasing the number of chambers, and by reducing the diameter of the rotor, even only locally.

Pattern Collapse-Free Drying with Sacrificial Gap Fill Polymers

This work discusses pattern collapse-free drying by application of a sacrificial polymer during the semiconductor wafer cleaning process. The sacrificial polymer is dispensed onto the wafer, displacing the rinse liquid and subsequently dried to form a solid polymer fill within the patterned structure, providing both mechanical support and a means for dry polymer removal by either plasma or thermal exposure. Polymer film thickness, gap fill capability and removal rate are explored for plasma ashable and thermally removable polymer families.

Effect of Degraded Additives on Under-Fill TSV

In the past few years the 3D IC integration (3DI) stacking has emerged as a potentially novel approach for extending computing performance without the high cost of CMOS scaling. The 3DI stacking technology is thought to be the essential technology of the next generation high-end semiconductors which will provides improved performance, and reduced form factor for applications such as logic-memory integration, image sensors, MEMS, and LED. The through silicon via (TSV) is one of the main components for 3DI stacking. Copper plating has been used for TSV metallization due to its low resistivity, low cost, excellent plating efficiency, easy to integrate, excellent reliability and a unique bottom up fill capability in presence of additives in the plating bath. One of the major challenges in the TSV metallization by plating is embedded voids and underfill TSV. Among the many parameters in TSV plating; bath composition especially suppressor to accelerator ratio (S/A) significantly affects TSV under-fill. It has been seen that the additives also degrades over the shelf life aging depends on their storage condition. Since the degradation of both suppressor and accelerator is not happening in the same rate, the S/A ratio vary and thus found to be caused TSV under-fill. Fig. 1(a) shows a cross-section SEM image of a TSV plated with BKM bath additives for 1600s. In contrast, Fig. 1(b) and 1(c) shows cross-section SEM images those were plated with same amount of BKM accelerator but with 10% and 25% less suppressor than the BKM respectively. It can be seen that the growth of copper inside the TSV increased~ 33% (with 25% lower suppressor) than the POR without increase of Cu film thickness on side wall, Chamfers and field area. Similarly, for a given suppressor, the copper fill rate can also varied by varying the accelerator concentration. In this paper, we will describe how additives affect the TSV under-fill and correlate the TSV under-fill with degradation of additives during their shelf life aging. Fig. 1(a) Cross-section SEM image of a TSV deposited with BKM plating additives of accelerator and suppressor and plating process for 1600s. Fig.1 (b) and (c) shows cross –section SEM images of a TSV those were plated with same amount of BKM accelerator but 10 and 25% less suppressor respectively than the BKM condition but exactly same plating process and time as Fig 1a Figure 1

Computational Fluid Dynamics Analysis of Gerotor Lubricating Pumps at High-Speed: Geometric Features Influencing the Filling Capability

The paper presents an extensive analysis of the influence on the suction capacity of the main geometric parameters of gerotor lubricating pumps. The study was carried out using a computational fluid dynamics (CFD) model developed with the commercial software PumpLinx®. The model of a reference gerotor unit was validated experimentally in terms of delivered flow rate in different operating conditions, in open and closed circuit configuration. In the former case, different geometries of the inlet pipe were tested. In the latter, the influence of the suction pressure at constant speed was analyzed. After the model validation, several geometric features were changed to assess their influence on the volumetric efficiency in conditions of incomplete filling, such as the thickness and the diameter of the gears, the position of the inlet pipe with respect to the rotors (radial, axial, and tangential), and the shape of the port plate.

Smart Hybrid Polymers for Advanced Damascene Electroplating: Combination of Superfill and Leveling Properties

AbstractA successful bottom‐up fill of single Damascene test features is achieved by using a two‐component additive package consisting of bis‐(sodium‐sulfopropyl)‐disulfide (SPS) and Imep polymers (polymerizates of imidazole and epichlorohydrin). In addition, a remarkable leveling effect is observed. Clearly, the Imep additive combines bottom‐up fill capabilities with leveling characteristics in one single polymer component. These unique hybrid properties of the Imep are rationalized on the basis of an extended N‐NDR (N‐shaped negative differential resistance) being present in the linear‐sweep voltammogram of the SPS/Imep additive system during Cu electrodeposition.

ALD W Metal Gate CMP

Beyond 32nm node, gate last integration scheme had become a mainstream because it ensures the thermal stability of high-kand metal gate stack by applying the metal gate after the high temperature source/drain activation anneal. During HKMG gate last CMOS integration, metal gate chemical and mechanical planarization (CMP) is an indispensable and key process step. Al metal gate is firstly introduced from 32nm node by Intel, which brought new process challenges for Al filling and correspondent CMP. We adopted W as metal gate using atomic layer deposition (ALD) method, besides of ALD W ideal fill capability, compatibility with traditional W CMP is also taken into account.Different ALD W layers were prepared using B2H6 base and SiH4 base. Removal rate, surface roughness and electrochemical characteristic in W slurry were examined for two types ALD W. The removal rate of B2H6 base ALD W was high than that of SiH4 base. RMS of ALD W with SiH4 and B2H6 base were all less than 1nm after CMP. The adhesion of SiH4 base ALD W between W and barrier layer was stronger than that of B2H6 base ALD W. B2H6 base ALD W has better filling ability than that of SiH4 base ALD W for small size gate trench. Compared with single base ALD W filling metal gate, B2H6 base ALD W filling with SiH4 base ALD W pre-treatment was more benefit to decrease metal gate dishing after CMP process.

A Proprietary Chemical Bath Life Study in MHM ULK Scheme Wet Cleaning

As technology evolves to 45nm and beyond, IC companies adopt TiN metal hardmask instead of PR (photo resist) to gain better etching profile, CD uniformity and less low-k material damage. To improve Cu gap fill capability, an in situ TiN pull back is needed in the subsequential wet clean step. This pullback can be done by mixing some additive with clean media, like H2O2. But H2O2 tends to decompose along the time, it also bring the challenges to the wet clean media stability. In this paper, we study a proprietary wet clean chemical behavior with pH, Cu ion concentration, H2O2 additive and bath lifetime. Cu ions content is demonstrated critical to the mixture instability when H2O2 presents. Chemical degradation mechanism is also discussed.

Effective Approach for TSV Cu Plating Gap Fill Improvement

TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.

Ultra-Low Copper Baths for Sub-35 nm Copper Interconnects

The copper interconnect technology is constrained by the non-uniformity of the current distribution over the wafer due to the terminal effect for resistive thin seeds. As a result, the current in the wafer center becomes insufficient to cathodically protect the copper seed leading to seed corrosion in this wafer area. To improve the current distribution, the exchange current density can be lowered e.g. by lowering the Cu2+ concentration. Our approach is to investigate and develop acid ultra-low copper baths with feature fill capability. For this goal, the optimum additives concentrations were sought and fill studies in 30 nm wide trenches were performed. Additionally, a low-copper/high-acid chemistry, that is also compatible with direct plating, was developed to enable the in-situ copper seed formation and filling in one process step for plating on non-copper seeds.

Ultra-Low Copper Baths for Sub-35nm Copper Interconnects

The copper interconnect technology is constrained by the significant current distribution due to the terminal effect for resistive thin seeds. As a result, the current in the wafer center can become insufficient for cathodic protection of thin copper seeds leading to center seed corrosion. To improve the current distribution, the exchange current density can be lowered e.g. by lowering the copper concentration. Our approach is to investigate and develop acid ultra-low copper baths with feature fill capability. For this goal, the optimum additives concentrations were sought and fill studies in 30 nm trenches were performed. In addition, proposing a high acid chemistry that is also compatible with direct plating, would enable the in-situ copper seed formation and filling in one and the same process step for direct plating on non-copper seed.

Effects of Resist Thickness and Viscoelasticity on the Cavity Filling Capability in Bilayer Thermal Embossing

Poly(methyl methacrylate) (PMMA) bilayer structures are employed as resists to investigate deformation of polymers by microthermal embossing. Owing to the dispersion of Fe3O4 particles in the upper layer, the distinct interface profiles of each layer resist can be observed by scanning electronic microscope (SEM). Deformation and replication fidelity are attributed to a variety of factors in the imprinting process. In particular, the thickness of each resist layer and the viscoelasticity of different molecular weight polymers play the most crucial roles among these factors. Based on experimental results, we improved the deformation models of imprinting for bilayer PMMA material and evaluated the models via specific parameters: the degree of deformation of the lower layer (DL), the fraction of cavity filling of the lower layer (FL), and variation in the fraction of the upper layer thickness (Ki). The final pattern of the upper or lower layer may be implicated in micro electro mechanical systems (MEMS).

Effects of Resist Thickness and Viscoelasticity on the Cavity Filling Capability in Bilayer Thermal Embossing

Effects of Resist Thickness and Viscoelasticity on the Cavity Filling Capability in Bilayer Thermal Embossing

Impact of “terminal effect” on Cu electrochemical deposition: Filling capability for different metallization options

The 300 mm wafer copper electrochemical deposition (ECD) process for dual damascene metallization of semiconductor advanced interconnects is critically reviewed and the breakthroughs that enable further scaling of this process are examined. Special emphasis is placed on analyzing the critical issues, such as barrier/seed options, terminal effect and future plating prospects for this technology. The smallest plateable feature size values are estimated for different metallization integration schemes, such as conventional Physical Vapor Deposited (PVD) TaN/Ta/Cu, hybrid RuTa/Cu, CuMn (8%) self-forming barrier/seed, and Plasma-Enhanced Atomic Layer Deposition (PEALD) Ru, limiting the allowed maximum sheet resistance to 14 Ohms/sq for the Cu-based seeds and the effective maximum filling aspect ratio to 5–6.

Transformation of hydrogen silsesquioxane properties with RIE plasma treatment for advanced multiple-gate MOSFETs

Keeping in line with Moore's law requires increasing efforts in the development of alternative electronic devices. Multiple-gate transistors are very promising in order to suppress short-channel effects and to increase the current drive. Nevertheless, the fabrication of such devices represents a strong challenge for silicon process technology. One of the key steps of the process consists in shrouding the silicon fins in an isolating matrix, using a flowable oxide, namely hydrogen silsesquioxane (HSQ). The general objective of this work is to show that the properties of HSQ can be modified by appropriate thermal or plasma treatments to modulate its characteristics in terms of etching selectivity and surface topography. SEM characterization has shown that HSQ exhibits excellent planarization and gap fill capabilities, while AFM analysis, on 100 nm thick HSQ films deposited by spin on, reveals a roughness as low as 3 nm. Various oxygen plasma treatments have been applied to densify the HSQ films. Fourier transform infra-red spectroscopy (FT-IR) has shown very interesting qualitative and quantitative informations. Chemical and physical transformations from a Si–O–Si cage-like structure into an Si–O–Si network one have been observed. It is shown that exposure to oxygen plasma at high power (290 W) for a long time (20 min) or thermal curing at high temperature improves the resistance to wet etching using 1% hydrofluoric acid (HF). This densification technique holds the remarkable property to transform HSQ into an SiO 2-like structure.

The use of electroless copper seed in electrochemical deposited copper interconnect

Copper (Cu) electroplating (EP) process requires a Cu seed to conduct the current. Conventional physical vapor deposition (PVD) seed suffers from poor step coverage while chemical vapor deposition (CVD) seed is cost-ineffective. We therefore propose the use of electroless (EL) technique as a Cu seed deposition method and demonstrate its integration with conventional Cu EP. The EL seed has excellent step coverage which when combined with the bottom-up fill capability of additives-based EP process, produces void-free fill. The EL seed-EP Cu film stack has good resistivity, roughness and acceptable (111) texture. However, some adhesion issues remain to be solved for this integration scheme.

Characterization of electroplated copper films for three-dimensional advanced packaging

A study was carried out to determine the feasibility of using the Cu electroplating process to achieve good gap fill in interchip-via (ICV) wafers, focusing on the effect different current wave forms have on electroplated Cu film properties, the gap fill capability and the chemical mechanical planarization process. It was found that the roughness of direct current (dc)-plated Cu films is at least three times lower than that of pulse-plated films and the roughness of the latter was observed to be strongly dependent on the magnitude of forward (If) and reverse (Ir) currents. This produced a significant difference in reflectivity between the two types of films. The as-deposited dc- and pulse-plated Cu films were also found to have specific resistivities of ∼2.2 and ∼2.1 μΩ cm, respectively. They were reduced to a similar value of 1.77 μΩ cm after annealing at 200 °C. All the dc and higher If pulse-plating processes produced Cu films having an average polish rate of 7000 Å/min with the polish rate U% less than 3%, showing a fluctuating profile across the wafer. The higher Ir pulse-plated film showed a very low polish rate of 210 Å/min with the polish rate U% at 58%, resulting in a dome profile. The multistep dc plating process was found unsuitable for the filling of large vias in the ICV wafers as it resulted in conformal plating with a large center seam being seen due to the pinch-off effect at the top of the via. The pulse-plating process showed a significant improvement in the gap fill capability with a reduction in the size of the center void. The pinch-off effect was also greatly reduced when higher Ir was used and an increase in bottom coverage could also be seen, resulting in acceptable gap fill with only a small center void in the ICV wafers.

Electrochemical aspects of new materials and technologies in microelectronics

Major scaling issues, which need to be addressed to continue scaling according to Moore’s law, include increase of transistor leakage due to use of thin gate oxide (about 1 nm limit for SiO 2), power (reaching 100 W/cm 2) and RC delay (dielectric constant limit is 1 for air and Cu resistivity increases with scaling down the feature sizes). Integration of new materials and technologies will allow us to continue scaling and improve device performance. Examples of new materials include high- k dielectrics and strained silicon in the frond end of wafer processing, low- k carbon-doped oxide and electroplated copper in the back end of wafer processing as well as electroplated bumps, high thermal conductivity interface, heat sink and heat spreader materials in packaging. Electrochemical technologies will play an increasingly important role in silicon technology due to low cost, use of self-assembly processing and self-aligned growth ability. New electrochemical technologies in silicon processing include copper electroplating (replaced Al interconnect to reduce RC delay and increase reliability), bump electroplating (replaced wire bonding to allow increased I/O and improve reliability), and porous silicon for silicon on isolator fabrication (to reduce transistor leakage). Copper electroplating allows a low R, an excellent gap fill capability and superior materials properties with (111) textured Cu films and large grain size, and a stable and controlled process.

57.3: Transparent Silicon‐based Low‐k Dielectric Materials for TFT‐LTPS Displays

AbstractSilsesquioxane resins are of particular interest for use as insulator materials in flat panel display applications due to their balance of electrical, optical, and mechanical properties. In this study, a series of HSQ and MSQ resins were synthesized and characterized in terms of their structures and thin film properties. These resin systems yielded high quality thin films with high modulus, good adhesion to silicon and glass substrates, high optical transparency (>98 % @ 300 − 800 nm), good planarization properties, excellent gap fill capability, good thermal and chemical stability to various photoresist and ITO etch chemicals necessary for the fabrication of flat panel displays.