Electrochemical aspects of new materials and technologies in microelectronics

Abstract

Major scaling issues, which need to be addressed to continue scaling according to Moore’s law, include increase of transistor leakage due to use of thin gate oxide (about 1 nm limit for SiO 2), power (reaching 100 W/cm 2) and RC delay (dielectric constant limit is 1 for air and Cu resistivity increases with scaling down the feature sizes). Integration of new materials and technologies will allow us to continue scaling and improve device performance. Examples of new materials include high- k dielectrics and strained silicon in the frond end of wafer processing, low- k carbon-doped oxide and electroplated copper in the back end of wafer processing as well as electroplated bumps, high thermal conductivity interface, heat sink and heat spreader materials in packaging. Electrochemical technologies will play an increasingly important role in silicon technology due to low cost, use of self-assembly processing and self-aligned growth ability. New electrochemical technologies in silicon processing include copper electroplating (replaced Al interconnect to reduce RC delay and increase reliability), bump electroplating (replaced wire bonding to allow increased I/O and improve reliability), and porous silicon for silicon on isolator fabrication (to reduce transistor leakage). Copper electroplating allows a low R, an excellent gap fill capability and superior materials properties with (111) textured Cu films and large grain size, and a stable and controlled process.