Field Programmable Gate Array Kit Research Articles

Field programmable gate array implementation of edge detection system based on an improved sobel edge detector

<p>Field programmable gate array (FPGA) is an integrated circuit consisting of internal hardware blocks with programmable link connections for users to customize operations for a particular application. Link connections can be easily reprogrammed, allowing the FPGA to adapt to changes to the design or even support a new application throughout the department's uptime. One of the important tasks in image processing is image edge detection image, with computer aided, image recognition is concerned with the recognition and classification of objects in an image, so edge detection is an important tool. In this paper, we design filter for edge detection in image processing using FPGA kit. We analysis and implementation of algorithm for image processing on FPGA, load the code and run the results. Comparative analysis with images processed by MATLAB software.</p>

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design of CRC circuit for 5G system using VHDL

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.

Design and Implementation of a Multiplier free FPGA based OFDM Transmitter

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of the implemented blocks (VHDL code) and compare them with corresponding results from simulation system implemented in matlab 2010a. The results of these practical tests show that the suggested approach gives a significant improvement in reducing complexity and processing delays (45 nsec) in comparison with the conventional implementations of OFDM transmitter.

Design and implementation of portable electrocardiogram recorder with field programmable gate arrays and IoT interface

The electrical activities of the heart are used to monitor cardiovascular diseases. It can be measured using electrocardiogram (ECG), a simple, painless test that can be recorded graphically. The physician, to predict the patient’s heart conditions and recommend suitable treatments, uses electrodes placed on the patient’s skin surface, to record these signals. The P, Q, R, S, T waves in the ECG signal can be used to determine the normality and abnormality of the heart's condition. The time interval differs for each cardiovascular condition of the heart. In this work, the ECG signal is acquired real-time using an intelligent sensor module, and the recorded value is processed to find the peak values. The data is sent to the web serverusing internet of things technology at a minimal time, where the physician can view it and proper decision can be taken. The real-time ECG data acquisition is also made using the field programmable gate array kit as it is a low cost, high-speed device and the output is viewed in the computer. The developed model is validated through MATLAB software and implemented for real-time applications.

Functional validation of highly synthesizable voltage comparator on FPGA

In the present work, a methodology has been proposed to design analog/mixed-signal circuits using digital-in-concept circuits in digital technology. This paper presents a digital standard cell-based, scalable, highly synthesizable analog voltage comparator designed in 180 nm CMOS technology at the supply voltage of 1.8 V. The digital design requires less design effort and is highly immune to process, voltage and temperature variations. The proposed comparator has been designed and simulated in the Cadence virtuoso analog design environment. It is observed from the simulation results that the total power dissipation and propagation delay is 143.2 μW and 1.07 ns, respectively. The offset voltage of the proposed comparator is 4.98 mV. Also, as a proof-of-concept, the feasibility of the proposed analog voltage comparator is carried out on Artix-7 field-programmable gate array (FPGA) using Xilinx Basys-3 FPGA kit and other off-the-shelf components. The proposed digital-in-concept comparator is suitable for low power and high-speed SoC application with reduced design effort and lesser time-to-market.

FPGA Realization of ANFIS Controller Using a Proposed Digital Design

The design and realization of Adaptive Neuro-Fuzzy Inference System (ANFIS) controller based on Field Programmable Gate Array (FPGA) is presented in this paper. The controller intended to control the temperature of medical oven. A novel design of digital ANFIS is presented here for the implementation process. Different controllers are designed and their results are compared using MATLAB program to show the ANFIS superiority. The designed controllers tested for cell cultures application at 37.5. A reduction is made for the designed digital ANFIS due to the used FPGA limitations. The reduced design minimizes the utilized slices from 366% to 3% and LUTs from 364% to 3%. The reduced design reached an optimum size for this controller to utilize a smallest memory size. A real-time FPGA implementation of the proposed digital ANFIS have been done and verified through Xilinx ISE 14.6 using the VHDL language. The VHDL code for the controller is produced, aggregated and downloaded on the FPGA Spartan 3A/AN FPGA kit. A comparison between the simulation and implementation results is made. The matching between these results proves the effectiveness and robustness of the proposed digital ANFIS and the excellent performance of the FPGA based controller.

Design and Implementation of Hardware to Perform Testing the Matching Packet Header Based on FPGA

The hardware architecture of the parallel process multiple RAM that emulates the behaviors of content addressable memory for packet classification is presents in this paper. With the increase in Internet networks’ speed, the speed of detection of intruders has become a basic requirement. In this work, a packet header field is used in a fast and efficient way to detect intruders to prevent them from accessing the data. The application test results were fast and compatible when used FPGA board technique from xilinx. Finally, the design, synthesis of this parallel process multiple RAM packet header detector has been achieved using Vivado 2018.2 simulator, and coding is written in Verilog HDL language and implemented on Virtex – 7 FPGA (Field Programmable Gate Array) kit.

Generic model implementation of deep neural network activation functions using GWO-optimized SCPWL model on FPGA

The implementation of non-linear Activation Functions (AFs) within the Artificial Neural Network (ANN) on the Field Programmable Gate Array (FPGA) is substantial due to the various applications it performs. Accuracy, speed and complexity are the most crucial factors considered in this implementation. Building non-linear AFs in a reconfigurable ANN requires either sequential operations and/or additional complexity. In this paper, a generic model for three types of non-linear AFs (Logistic sigmoid (LogSig), Tan sigmoid (TanSig) and Radial Basis Function (RBF)) has been designed based on Simplicial Canonical Piecewise Linear (SCPWL) model that is optimized using Grey Wolf Optimizer (GWO(Algorithm. The designed model has been achieved by nine segments of the SCPWL model. The input of the AFs is ranging from (−8 to 8). Matlab has been deployed to design, optimize, simulate and validate this model. The maximum errors were 5.2e−3, 15.4e−3 and 7e−3 for LogSig, TanSig and RBF respectively. And, the Mean Square Error (MSE) were 1.81e−6, 1.22e−5 and 1.42e−5 for LogSig, TanSig and RBF respectively. The Matlab/HDL Coder has been used to generate the VHDL codes. The Xilinx Arty A7 (Xc7a35ticsg324-1L) FPGA kit is used to validate the designed model on Vivado Design Suite software. It has been noticed that it takes 581 Look-Up Tables (LUTs), nine DSP slices and a delay of (35.346 ns) to implement the nine SCPWL segments for any linear and non-linear AF. For validation, a complete ANN has been built with three hidden layers, each layer contain with one of the proposed AF models.

Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA.

3D Stereo Rendering Using FPGA

Stereo rendering presents a virtual 3D scene from two slightly different vantage points. It is of great importance in the field of machine vision, robotics and image analysis. This paper proposes a stereo vision system that is realized in a single field programmable gate array (FPGA). Calculations of the stereo pairs are made by using two-center projection (off-axis) method. The first red resultant image is for left eye while the second blue one is for right eye; the 3D illusion is produced when looking to them using anaglyph. This computer graphic hardware system is implemented using Spartan3E XC3S500E FPGA kit. The execution time for the proposal is 1266 faster than OpenGL time with maximum operating frequency of 35.417 MHz, while the max occupation area reaches 84%. Keywords: Computer Graphic; Stereoscopic; anaglyph; FPGA; two-center projection ;Off-axis Method; stereo pairs. DOI : 10.7176/CEIS/10-3-04 Publication date : April 30 th 2019

HIL Co-Simulation of Finite Set-Model Predictive Control Using FPGA for a Three-Phase VSI System

The conversion and control for the utilization of power generated from energy sources can be performed using a power electronic converter system. The voltage source inverter (VSI) is one of the commonly used converter topologies, being controlled by a switching control algorithm for power conversion. Finite set-model predictive control (FS-MPC) is a modern switching control algorithm and has received significant attention due to its predictive nature. In this paper, the implementation of FS-MPC is presented for the load-side current control of a three-phase VSI system using an integrated platform of MATLAB/Simulink and Xilinx system generator (XSG). The XSG provides the functionality of digital design and intuitive implementation of field-programmable gate array (FPGA) controlled systems. The additional functionality of hardware-in-the-loop (HIL) co-simulation using FPGA is used for the testing and validation of controller performance. The controller performance is validated through three platforms: MATLAB/Simulink, XSG and HIL co-simulation using ZedBoard Zynq evaluation and development FPGA kit.

Efficient Coding Architectures for Reed–Solomon and Low-Density Parity-Check Decoders for Magnetic and Other Data Storage Systems

High-performance error correction codes are used in high-density data storage devices to overcome noise and channel impairments. In this paper, we develop novel and efficient decoding architectures for Reed-Solomon (RS) and low-density parity-check (LDPC) codes that are used in almost all data storage devices. First, we present a high-speed low-latency hard-decision-based pipelined RS decoder architecture that computes the error locator polynomial in exactly 2t clock cycles without parallelism. The RS decoder is a two-stage pipelined engine operating at the least latency possible, thereby, significantly reducing the size of the delay buffer. The RS decoder is implemented using Cadence tools and Kintex-7 field programmable gate array (FPGA). The technology-scaled normalized throughput of the pipelined RS decoder is almost two times compared with the existing decoders. The overall processing latency is reduced by almost 80% compared with the existing designs. Second, we design a high-throughput LDPC decoder using layered and non-layered min-sum algorithm based on non-uniform quantization (NUQ) on an FPGA kit. Unlike the standard state-of-the-art uniform quantization used in virtually all decoder circuits, our NUQ technique: 1) achieves a slight performance improvement of similar to 0.1 dB in the signal-to-noise ratio using equal number of bits and 2) yields 20% area savings (using 1 bit less) for the block RAMs used for storing intermediate check node and variable node messages.

Frequency Analysis of 32-bit Modular Divider Based on Extended GCD Algorithm for Different FPGA chips

Modular inversion with large integers and modulus is a fundamental operation in many public-key cryptosystems. Extended Euclidean algorithm (XGCD) is an extension of Euclidean algorithm (GCD) used to compute the modular multiplicative inverse of two coprime numbers. In this paper, we propose a Frequency Analysis study of 32-bit modular divider based on extended-GCD algorithm targeting different chips of field-programmable gate array (FPGA). The experimental results showed that the design recorded the best performance results when implemented using Kintex7 (xc7k70t-2-fbg676) FPGA kit with a minimum delay period of 50.63 ns and maximum operating frequency of 19.5 MHz. Therefore, the proposed work can be embedded with many FPGA based cryptographic applications.

Design and field programmable gate array implementation of cascade neural network based flux estimator for speed estimation in induction motor drives

This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives. The main focus of this study is the FPGA implementation of cascade NN based flux estimator. The major issues in FPGA implementation are optimisation of cost (resource) and execution time. A simple non-linear activation function called as Elliott function is used to reduce the execution time. To reduce the cost, and effectively utilise resource, the concept of layer multiplexing is adopted. The lowest bit precision needed for good performance of the estimator is identified and implemented. The proposed NN based flux estimator using simple excitation function and minimum bit precision is implemented using layer multiplexing technique. The designed estimator is tested on Spartan FPGA kit (3sd1800afg676-4) and the results obtained are presented.

Real Time Object Tracking using FPGA Development Kit

The main idea of this work is object tracking using real time video processing. For this purpose we designed an embedded system that performs the object tracking algorithm for accurate tracking of defined object. The theme may be implemented for the security companies, sports and the armed forces to make them more equipped and advanced. The heart of the system is a Field Programmable Gate Arrays development kit. It controls the whole system by receiving the video signal from camera, processes it and sends the video signal to the Liquid Crystal Display or monitor. After receiving video of intended object, target selection is performed to select the target to track and then the tracking algorithm is implemented using image processing algorithms implemented using Field Programmable Gate Arrays development kit. We also interfaced the DC gear motor to control the movement of the camera in order to track the selected object. In order to design the standalone application we transformed our algorithm in Field Programmable Gate Array kit.

FPGA based Smart Wireless MIMO Control System

In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

FIR Filter Designing using Xilinx System Generator

System generator is used to design efficient DSP algorithm on FPGA. In this paper Finite Impulse Response (FIR) filter is designed using Simulink in Xilinx System generator. The filters have been designed using Distributed Arithmetic (DA) Algorithm. This design has been further synthesized on Xilinx Virtex-4 FPGA kit. Finally comparison is done between the results obtained from the software simulations and those from FPGA using hardware co-simulation. KeywordsImpulse Response (FIR), Distributed Algorithm (DA), Field Programmable Gate Array (FPGA), Digital Signal Processing (DSP), Analog-to-Digital Converter (ADC).

Design and VLSI implementation of power efficient processor for object localisation in large WSN

The presence of multiple obstacles on the real deployed geographical area may hinder the effective operations of large scale wireless sensor network in terms of significant disturbance in proper routing, increased delay in data transmission and increased energy consumptions. To overcome this problem, a novel pulse mode object localisation algorithm and its VLSI implementation for designing the sensor node processor is proposed in this article. The algorithm supports distributed and energy efficient sleep scheduling with periodic synchronisation and reconfigure the routing scheme that can be used to extend the life time of sensor network. The algorithm is made power efficient by using pulse mode operation. It is a high performance sensor node processor with an overall power consumption of 0.012 mW in active mode with a dynamic current of 1.27 mA at the working frequency of 1,536 MHz. The algorithm is verified using MATLAB for different possible obstacles and percentage error has been calculated for each case. The hardware of this sensor node processor has been realised using ISE 14.3 simulation tools and emulated in Virtex-V prototype field programmable gate array kit.