Functional validation of highly synthesizable voltage comparator on FPGA

Abstract

In the present work, a methodology has been proposed to design analog/mixed-signal circuits using digital-in-concept circuits in digital technology. This paper presents a digital standard cell-based, scalable, highly synthesizable analog voltage comparator designed in 180 nm CMOS technology at the supply voltage of 1.8 V. The digital design requires less design effort and is highly immune to process, voltage and temperature variations. The proposed comparator has been designed and simulated in the Cadence virtuoso analog design environment. It is observed from the simulation results that the total power dissipation and propagation delay is 143.2 μW and 1.07 ns, respectively. The offset voltage of the proposed comparator is 4.98 mV. Also, as a proof-of-concept, the feasibility of the proposed analog voltage comparator is carried out on Artix-7 field-programmable gate array (FPGA) using Xilinx Basys-3 FPGA kit and other off-the-shelf components. The proposed digital-in-concept comparator is suitable for low power and high-speed SoC application with reduced design effort and lesser time-to-market.