Design and Implementation of Hardware to Perform Testing the Matching Packet Header Based on FPGA

Abstract

The hardware architecture of the parallel process multiple RAM that emulates the behaviors of content addressable memory for packet classification is presents in this paper. With the increase in Internet networks’ speed, the speed of detection of intruders has become a basic requirement. In this work, a packet header field is used in a fast and efficient way to detect intruders to prevent them from accessing the data. The application test results were fast and compatible when used FPGA board technique from xilinx. Finally, the design, synthesis of this parallel process multiple RAM packet header detector has been achieved using Vivado 2018.2 simulator, and coding is written in Verilog HDL language and implemented on Virtex – 7 FPGA (Field Programmable Gate Array) kit.