FIR Filter Designing using Xilinx System Generator

Abstract

System generator is used to design efficient DSP algorithm on FPGA. In this paper Finite Impulse Response (FIR) filter is designed using Simulink in Xilinx System generator. The filters have been designed using Distributed Arithmetic (DA) Algorithm. This design has been further synthesized on Xilinx Virtex-4 FPGA kit. Finally comparison is done between the results obtained from the software simulations and those from FPGA using hardware co-simulation. KeywordsImpulse Response (FIR), Distributed Algorithm (DA), Field Programmable Gate Array (FPGA), Digital Signal Processing (DSP), Analog-to-Digital Converter (ADC).