Field Programmable Gate Array Logic Research Articles

Design of an FPGA-Based Fuzzy Feedback Controller for Closed-Loop FES in Knee Joint Model.

Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb’s movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application.

Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

SummaryStatistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the interpolation filter on field‐programmable gate array (FPGA) based on Xilinx setup environment. In a second step, a Hardware/Software (HW/SW) co‐design implementation of HM16.7 encoder is performed on Zynq MPSoC platform to evaluate the proposed interpolation filter IP in terms of total encoder run‐time, taking advantages of both processing units (quad‐core ARM Cortex TM‐A53 processor and Programmable Logic FPGA component) available on the Zynq MPSoC. The proposed architecture of luma and chroma filters was simulated and synthesized on Xilinx XCZU7EV‐2FFVC1156 FPGA at 250‐MHz clock frequency. The synthesis results present an optimized power consumption of 3.308 mW for higher resolutions (2560 × 1600 and 1920 × 1080) at 50 fps with the use of just 1% of the FPGA resources. The experimental results of the co‐design implementation of HEVC encoder present a speedup of 2 times (41% in PeopleOnStreet sequence) in terms of processing time compared to the software alone implementation, with a an increase of 0.51% of bit rate and a very small degradation of peak signal‐to‐noise ratio (PSNR) (0.01%).

Precision-Improved Pulsed Laser Ranging by Multidelayed Echo Signals Triggering

We propose a pulsed laser ranging method based on a multiecho delay trigger, which improves the precision of pulsed laser ranging. A signal delay unit is used to accurately delay the pulse-echo signal. In a fixed time window, the echo delay pulse triggers the laser transmitter to generate pulsed laser light; meanwhile, the counter records several echo pulses received, and then, the actual distance can be calculated. In terms of improving the ranging precision, this method overcomes the essential of higher time resolution time-to-digital converter (TDC) chip in traditional time-of-flight (TOF) pulsed laser ranging. The method can be realized by using a field-programmable logic gate array (FPGA) chip, a delay unit, and a set of laser transmitters and receivers, which makes the system structure simple and low cost. Experimental results show that this method can achieve more accurate distance measurement and significantly reduced error, to the best of our knowledge, which improves the pulsed laser ranging from centimeter- to millimeter-order precisions. We believe that this method has a promising application prospect in the field of high-precision pulsed laser ranging of fixed targets.

A Precise, Parallel and Scalable Measurement System for Ballistocardiographic Research

Ballistocardiography (BCG) is the measurement of heart and cardiovascular related acceleration of the body. Due to the availability of inexpensive and small accelerometers, scientific interest in BCG increased in recent years. A variety of different measurement systems have emerged. Many of them lack on data quality, such as resolution and temporal precision. A deterministic timing behaviour is essential to produce meaningful results, especially when dealing with data from multiple sensors at once. We present a novel measurement system, which allows for parallel digital data acquisition in the presence of strict deterministic timing constraints. A dedicated server manages multiple measurement boards and acts as a data sink. All connected boards are synchronized, which renders all acquired data comparable in time. On each board, data from 4 parallel channels is pre-processed and time-stamped in Field Programmable Gate Array logic. The presented system enables distributed measurements and is scalable within the limitations of the available network. A field test with over 30 subjects proved the usability and reliability of the system, while all data are made available for the community and first results of this campaign are presented within this paper.

Hardware Root-of-Trust-based integrity for shared library function pointers in embedded systems

Many security measures designed for large-scale compute hardware (e.g., workstations and servers) are not optimized for embedded systems. One such measure, Relocation Read-Only (RelRO), protects binary relocation sections from tampering after dynamic linking; however, RelRO depends on the presence of memory management hardware that not all embedded systems include. More generally, the latest hardware modifications to processor architectures may not always be available to provide security in small-scale embedded systems. In this paper, we propose another solution for relocation protection for use in embedded systems that have a field-programmable gate array (FPGA) on chip. Our solution prevents relocation section overwrites from diverting control flow as they would in an unprotected binary by implementing a hardware Root of Trust into which to store and out of which to retrieve shared library function pointers. We offer two system variations which provide designers with flexibility to choose a lighter or a more robust protection. We also demonstrate a proof of concept implemented on a popular FPGA development board and provide comparison with RelRO. Our work provides embedded system developers with a security measure like RelRO without requiring a customized memory management unit. Our work is useful on computer systems that include embedded reconfigurable logic on chip. The authors believe this is the first paper in which reconfigurable logic is used to provide security functionality previously implemented in a custom instruction set or other computer architecture modifications. Our work points toward a future where FPGA logic embedded on chip can be adapted to improve the security of software.

A high performance fast-Fourier-transform spectrum analyzer for measuring spin noise spectrums**Project supported by the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDC0702200), the National Key R&D Program of China (Grant Nos. 2018YFA0306600 and 2016YFB0501603), the National Natural Science Foundation of China (Grant No. 11927811), the Chinese Academy of Sciences (Grants Nos. GJJSTD20170001 and QYZDY-SSW-SLH004), Anhui

A high performance fast-Fourier-transform (FFT) spectrum analyzer, which is developed for measure spin noise spectrums, is presented in this paper. The analyzer is implemented with a field-programmable-gate-arrays (FPGA) chip for data and command management. An analog-to-digital-convertor chip is integrated for analog signal acquisition. In order to meet the various requirements of measuring different types of spin noise spectrums, multiple operating modes are designed and realized using the reprogrammable FPGA logic resources. The FFT function is fully managed by the programmable resource inside the FPGA chip. A 1 GSa/s sampling rate and a 100 percent data coverage ratio with non-dead-time are obtained. 30534 FFT spectrums can be acquired per second, and the spectrums can be on-board accumulated and averaged. Digital filters, multi-stage reconfigurable data reconstruction modules, and frequency down conversion modules are also implemented in the FPGA to provide flexible real-time data processing capacity, thus the noise floor and signals aliasing can be suppressed effectively. An efficiency comparison between the FPGA-based FFT spectrum analyzer and the software-based FFT is demonstrated, and the high performance FFT spectrum analyzer has a significant advantage in obtaining high resolution spin noise spectrums with enhanced efficiency.

Optimizing FPGA Logic Block Architectures for Arithmetic

Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the computer-aided design (CAD) flow. However, these choices have not been studied much and hence we explore a number of possibilities. We also highlight front-end elaboration optimization that helps ameliorate the restrictions placed on logic synthesis by hardened arithmetic. We show that hard adders and carry chains increase the performance of simple adders by a factor of 4 or more, but on larger benchmark designs that contain arithmetic improve the overall performance by 15%. Our results also show that for complete application circuits simple hardened ripple-carry adders perform as well as more complex carry-lookahead adders. Our best non-fracturable lookup table (non-fLUT) architecture with hardened arithmetic yields 12% better area-delay product than architectures without hardened arithmetic. We also investigate the impact of fLUTs and their interaction with hardened arithmetic. We find that fLUTs offer significant (12%-15%) area reduction, which is complementary to the delay reduction of hardened arithmetic. Therefore, our best fLUT architectures which use two bits of hardened arithmetic achieve 25% better area-delay product than non-fLUT architectures without hardened arithmetic.

Design and Development of Fast Protection and Fast Monitoring Module Compatible With NI Compact RIO System for ITER-India Gyrotron Test Facility

The ITER electron cyclotron (EC) system will have gyrotron sources used for plasma heating and current drive applications. During gyrotron operation, different faults may be encountered and in the case of critical faults, the High Voltage Power Supplies (HVPS) should be switched off in $ time scale, which otherwise could damage the internal components of a gyrotron tube. Also during the operation, the main operating parameters need to be acquired on fast time scales (~5 Msps) to know the gyrotron output characteristics. A solution is required catering to both the requirements, which should be cost-effective, and also comply with recommended hardware and software framework. In this context, a custom prototype module compatible with NI-CompactRIO (NI-cRIO) system is under development for ITER-India Gyrotron Test Facility (IIGTF). The module has protection and monitoring functions both in parallel in a single unit. It has a transmitter (TX) and receiver (RX) card connected optically to complete the link. The TX has fast sampling analog-to-digital converter (ADC), fast comparator, field-programmable gate array (FPGA), and an optical transmitter. The TX sends monitoring and trip information optically to the RX. The RX card has an optical receiver, FPGA, and digital-to-analog converter (DAC), which generates back the original signals. The heart of the module is FPGA logic, which performs encoding and decoding (as per 8b10b standard) of ADC serial data, thereby eliminating the use of any serial converter ICs. The module can be plugged into the cRIO chassis and also can be used as a standalone module. This article discusses the concept, design, development, and test results of fast protection and fast signal monitoring module

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs

Field-programmable gate array (FPGA)-based accelerators for convolutional neural network (CNN) inference have received significant attention in recent years. The reported designs tend to adopt a similar underlying approach based on multiplier-accumulator (MAC) arrays, which yields strong demand for the available on-chip DSP blocks, while leaving FPGA logic and memory resources underutilized. The practical outcome is that the computational roof of the accelerator is bound by the number of DSP blocks offered by the target FPGA. In addition, integrating the CNN accelerator with other functional units that may also need DSP blocks would degrade the inference performance. Leveraging the robustness of inference accuracy to limited arithmetic precision, we propose a transformation to the convolution computation, which leads to transformation of the accelerator design space and relaxes the pressure on the required DSP resources. Through analytical and empirical evaluations, we demonstrate that our approach enables us to strike a favorable balance between utilization of the FPGA on-chip memory, logic, and DSP resources, due to which, our accelerator considerably outperforms state of the art. We report the effectiveness of our approach on a variety of FPGA devices, including Cyclone-V, Stratix-V, and Arria-10, which are used in large number of applications, ranging from embedded settings to high performance computing. Our proposed technique yields 1.5x throughput improvement and 4x DSP resource reduction compared to the best frequency domain convolution-based accelerator, and 2.5x boost in raw arithmetic performance and 8.4x saving in DSPs compared to a state-of-the-art sparse convolution-based accelerator.

Design and Verification of SDRAM Controller Based on FPGA

SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.

Resource-Efficient Image Buffer Architecture for Neighborhood Processors

Neighborhood image processing operations on Field Programmable Gate Array (FPGA) are considered as memory intensive operations. A large memory bandwidth is required to transfer the required pixel data from external memory to the processing unit. On-chip image buffers are employed to reduce this data transfer rate. Conventional image buffers, implemented either by using FPGA logic resources or embedded memories are resource inefficient. They exhaust the limited FPGA resources quickly. Consequently, hardware implementation of neighborhood operations becomes expensive, and integrating them in resource constrained devices becomes unfeasible. This paper presents a resource efficient FPGA based on-chip buffer architecture. The proposed architecture utilizes full capacity of a single Xilinx Block-RAM (BRAM36 primitive) for storing multiple rows of input image. To get multiple pixels/clock in a user defined scan order, an efficient duty-cycle based memory accessing technique is coupled with a customized addressing circuitry. This accessing technique exploits switching capabilities of BRAM to read 4 pixels in a single clock cycle without degrading system frequency. The addressing circuitry provides multiple pixels/clock in any user defined scan order to implement a wide range of neighborhood operations. With the saving of 83% BRAM resources, the buffer architecture operates at 278 MHz on Xilinx Artix-7 FPGA with an efficiency of 1.3 clock/pixel. It is thus capable to fulfill real time image processing requirements for HD image resolution ( $1080\times 1920$ ) @103 fps.

The VMM readout system

The New Small Wheel Upgrade of the ATLAS experiment at CERN, planned to take place at 2020, requires a new generation of front-end electronics that will support its data acquisition requirements. The VMM Application-Specific Integrated Circuit has been in development for the last seven years to serve as the foundation of the New Small Wheel’s readout scheme. It has gone through three major revisions and a minor one, the latter being the production version. To facilitate the testing and readout of the VMM, as well as to study its detector performance, a complete readout system has been developed. It consists of flexible Field-Programmable Gate Array logic with extensive functionality, and an efficient software framework providing the user interface. This system, referred to as the ”The VMM Readout System”, has been used in test-beam campaigns at CERN, as well as in bench calibration and testing measurement scenarios for the past several years, supporting all readout modes and features of the VMM.

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area or increase throughput. However, these benefits come at the cost of a decrease in accuracy. In this article, we demonstrate that reconfigurable constant coefficient multipliers (RCCMs) offer a better alternative for saving the silicon area than utilizing low-precision arithmetic. RCCMs multiply input values by a restricted choice of coefficients using only adders, subtractors, bit shifts, and multiplexers (MUXes), meaning that they can be heavily optimized for FPGAs. We propose a family of RCCMs tailored to FPGA logic elements to ensure their efficient utilization. To minimize information loss from quantization, we then develop novel training techniques that map the possible coefficient representations of the RCCMs to neural network weight parameter distributions. This enables the usage of the RCCMs in hardware, while maintaining high accuracy. We demonstrate the benefits of these techniques using AlexNet, ResNet-18, and ResNet-50 networks. The resulting implementations achieve up to 50% resource savings over traditional 8-bit quantized networks, translating to significant speedups and power savings. Our RCCM with the lowest resource requirements exceeds 6-bit fixed point accuracy, while all other implementations with RCCMs achieve at least similar accuracy to an 8-bit uniformly quantized design, while achieving significant resource savings.

Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect

This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides very high-density interconnects (currently in the range of 500–1000 I/O/mm) localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected. The construction of the silicon bridge and the package to allow high BW electrical signaling between two dies is discussed in detail. Examples of the EMIB implementations for the links between the field-programmable gate array (FPGA) logic and high bandwidth memory generation 2 (HBM2) memory stacks, graphics die and HBM2 memory stacks, FPGA logic die, and high-performance transceiver die are described. EMIB packaging is compared with similar high-density interconnect technologies such as silicon interposer with through-silicon vias (TSVs) and other fan-out-based package technologies. Design optimization strategies for power delivery and I/O routing in the presence of an embedded bridge are highlighted.

Cavity Simulator for European Spallation Source

European Spallation Source (ESS) will be the brightest neutron source in the world. It is being built in Lund, Sweden. Over 120 superconducting cavities will be installed in the facility, each regulated by an individual low-level radio frequency (LLRF) control system. To reduce the risk of testing the systems on real cavities, a cavity simulator was designed. It reproduces the behavior of superconducting cavities used in the medium and high beta sections of ESS's Linac. The high power RF amplifier and piezo actuators parameters are also simulated. Based on the RF drive and piezo control signals, the cavity simulator generates the RF signals acquired by the inputs of the LLRF control system. This is used to close the LLRF feedback loop in real time. The RF front end of the cavity simulator consists of vector modulators, down-converting circuits, and a set of fast data converters. The cavity response simulation is performed in a high-speed field programmable gate array logic by a dedicated firmware that was optimized to minimize the processing time. The device also generates clock, local oscillator, and the 704.42-MHz reference signals to allow for system tests outside of the accelerator environment. In this paper, the design of the cavity simulator, description of the algorithms used in the firmware, and measurement results of the device are presented.

OpenCL Implementation of an Adaptive Disruption Predictor Based on a Probabilistic Venn Classifier

The ability and flexibility of the open computing language (OpenCL) for task parallelization in heterogeneous computing platforms [field-programmable gate array (FPGA), CPU, and GPU] are remarkable advantages when designing advanced data acquisition and processing systems. The use of FPGA devices in data acquisition devices increases the capabilities of traditional data acquisition systems, thus allowing the implementation of complex mathematical algorithms with the acquired data. This paper shows an OpenCL implementation of an adaptive probabilistic disruption predictor for fusion devices implemented in a Cyclone V SoC device with an ARM processor, the FPGA logic, and an analog to digital converter. This paper describes the methodology used, the hardware/software system architecture, and the implementation results. The work highlights the critical aspects involved in designing these OpenCL-based systems and, in particular, the implementation of the board support package. This paper also presents the aspects such as the significant differences in the design flow concept between FPGA and GPU OpenCL implementations and how to optimize the FPGA implementation with OpenCL. The results show that it is possible to make predictions with computation times shorter than $500~\mu \text{s}$ when using this low-cost SoC.

An FPGA-Based Hardware Platform for the Control of Spin-Based Quantum Systems

This paper reports the development of a highly efficient, flexible hardware platform, which is suitable for the control of spin-based quantum systems including quantum computation and quantum metrology. A two-channel arbitrary waveform generator (AWG), an eight-channel pulse/sequence generator, a two-channel analog-to-digital converter (ADC), and a two-channel high-speed time-to-digital converter (TDC) are fully integrated on a printed circuit board (PCB). The AWG has a 1-GSa/s sampling rate and a 16-bit amplitude resolution. The pulse/sequence generator can continuously output pulse/sequence signals with a 50-ps time resolution and a dynamic range from 5 ns to 2 s. The ADC provides a 1-GSa/s sampling rate and a 12-bit amplitude resolution for analog signal acquisition. The TDC provides a 6-ps time resolution and a maximum sampling frequency of 125 MHz. All these modules are realized utilizing a field-programmable gate array (FPGA). Customized data calculation modules are also implemented with the FPGA logic. The hardware was tested and implemented in a pulsed electron spin resonance (ESR) spectrometer and an optically detected magnetic resonance (ODMR) spectrometer.

Implementation of Low Power Null Conventional Logic Function for Configuration Logic Block

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

IFLEX: A Fully Open-Source, High-Density Field-Programmable Gate Array (FPGA)-Based Hardware Co-Processor for Vector Similarity Searching

Vector similarity searching consists of comparing a query vector against a high volume of entries in a reference data set, according to a chosen similarity metric such as the L1-norm, L2-norm, or Hamming distance. Large-scale research and commercial applications of these computations are developing rapidly across artificial intelligence fields as diverse as semantic text querying, retrieval of multimedia materials, and prediction of the properties of pharmacological molecules and engineered materials. While vector similarity searching is, at present, predominantly implemented on standard central processing unit (CPU) hardware running optimized indexing algorithms, the interest in massively-parallel computing architectures is increasing. Accordingly, a range of systems based on graphics processing units (GPU) and field-programmable gate arrays (FPGA) have been proposed; however, the availability of the design materials for these systems remains largely confined to a small number of corporations and research institutions. Here, we introduce a fully open-source hardware accelerator for vector similarity searching, based on an array of 21 FPGAs densely intertwined with 42 GB of high-speed dynamic memory and installed on a custom-designed compute node board, which yields an aggregate bandwidth of 33.6 GB/s and can be seamlessly reconfigured to implement nearly arbitrary distance calculations. A novel logic and software architecture, based on a lane-wise organization of independent engines implementing distributed distance calculation and sorting, allows attaining noteworthy query latency and power consumption performance on both single- and multi-node system configurations. The entire circuit board hardware, FPGA logic, and host software design is herein presented and freely provided for unlimited use, supporting open innovation and research in this area.