Field Programmable Gate Array Logic Research Articles

Development of All Solid State Nanosecond Pulse Transformer Fault Detection Device Based on Marx Circuit

Abstract a nanosecond pulse generator with a fast leading edge for transformer fault diagnosis is developed. The device is composed of a full solid-state nanosecond pulse generator based on Marx circuit and with a tail cut switch and a field programmable logic gate array (FPGA) device. Among them, the nanosecond pulse source is mainly composed of DC power supply, control circuit and main circuit. The main circuit is a 9-level modular Marx circuit, using MOSFET as the main switch and tail cut switch; The control circuit generates a synchronous trigger pulse signal, which drives the MOSFET to work synchronously after being isolated through the optical fiber. The output nanosecond pulse voltage parameters are adjustable amplitude 0-8kv, pulse width 100˜1000ns, repetition frequency 1hz˜1000hz, rising edge 30ns and falling edge 40ns. The transformer fault diagnosis platform is built, and the transformer off-line and on-line fault diagnosis is carried out, which paves the way for further exploration of transformer fault diagnosis technology.

Improving the exploitability of Simulated Adiabatic Bifurcation through a flexible and open-source digital architecture

Combinatorial Optimization (CO) problems exhibit exponential complexity, constraining classical computers from providing fast and satisfactory outcomes. Quantum Computers (QCs) can effectively find optimal or near-optimal solutions by exploring the solutions space of a problem encoded in a qubits system, exploiting principles of quantum mechanics. However, non-idealities and high costs limit their availability. These can be overcome by emulating QCs on cheaper and more accessible classical computing platforms, like Field-Programmable Gate Arrays (FPGAs). This article presents a digital architecture, implementing the Ising-compatible Simulated Adiabatic Bifurcation algorithm. It mimics the quantum adiabatic evolution of a network of non-linear Kerr oscillators. The architecture, described in VHDL and targeting FPGAs, consists of processing elements for computing the Kerr oscillators’ evolution, a set of units considering their Ising-related interactions and an evolution variables update unit. The proposed approach includes a speedup-targeting approximation of the algorithm, a method for handling single-variable constraints, and a software model that allows architecture customization for specific problems. Tests were conducted using an Altera Cyclone V SoC with FPGA logic and the Nios II processor for interface purposes. The results demonstrate the functionality of the architecture and its scalability with the problem size, making it suitable for real-world applications.

Modeling and simulation of three-phase IGBT full-bridge inverter circuit based on FPGA

The field of motor drive makes extensive use of electronic power modeling and simulation of three-phase IGBT full-bridge inverter circuits. The accuracy and computational efficiency of these models have a direct impact on the dependability of the motor control system. The majority of earlier research focused solely on static processes of turning on and off in IGBTs, disregarding the transient proesses that occur when three-phase IGBT full-bridge inverter circuits are switched at high frequencies. This has an impact on the circuits' accuracy in real-time simulation. Therefore, this paper proposes and builds a field-programmable logic gate array (FPGA)-based steady-state and transient dual-phase three-phase IGBT full-bridge inverter circuit model for the static and transient characteristics of the insulated gate bipolar transistor (IGBT) element in the circuit. Depending on whether or not the switching states of the six IGBTs in the three-phase IGBT full-bridge inverter circuit are altered, the simulation process is split into steady state and transient phases. In the steady state phase with large step size, the circuit is discretized using the binary L/C approach. In the transient phase, the transient process is divided into several small-step-long time domains. Real-time simulation waveforms are generated by interleaving and combining the multistage fitting method's solution of the circuit's transient waveforms at tiny step lengths with the steady state phase. Finally, in order to demonstrate the accuracy of the circuit model in this work, the simulation results of the two-stage three-phase IGBT full-bridge inverter circuit model based on FPGA are compared with those of the conventional ideal model for waveform comparison and data analysis.

A tunable hybrid metasurface design with integrated diffusion and absorption

AbstractIn this letter, a tunable hybrid metasurface (THMS) with electromagnetic switching characteristics based on the field‐programmable logic gate array (FPGA) is developed, which combines the mechanisms of both phase cancellation and absorption. Compared to other hybrid metasurface, the proposed design possesses two major functions of electromagnetic switching and dynamic tuning. By adjusting the bias voltage of the active components controlled by FPGA module, the in‐band tuning and active switching at different frequency bands of 3.63–5.57, 4.86–10.47, and 9.40–12.36 GHz can be obtained. A physical prototype with the size of 350 mm × 370 mm is fabricated and measured for verification, and the measurement shows that the monostatic radar cross section achieves varying degrees of reduction from 1.66 to 12.04 GHz.

An adaptive laser processing method of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level

Laser micro/nano processing exhibits significant advantages in manufacturing capability and performance. However, the properties of ablated materials cannot be sensed and identified during processing is an intractable challenge. In particular, multilayer heterogeneous materials often evolve into excessive residues and damages during laser selective removal. In this study, we developed an adaptive laser processing method that includes material interface adaptive and laser power adaptive for selective removal of multilayer heterogeneous materials by monitoring dynamic spectrum at kHz-MHz level. The mechanism of interface sensing and the threshold of laser selective removal of multilayer materials were investigated. Dual-channel parallel detection mode of the blazed grating with the ultrafast photodetector at the kHz-MHz pulse level has been designed and verified for monitoring adjacent layers synchronously. High-speed signals with a pulse width of 30 ns and a repetition frequency of 0–15 MHz were identified by the Field Programmable Logic Gate Array (FPGA), and pulse-level closed-loop feedback was finished. Patterned selective removal on an FR-4 copper clad laminate (CCL) and flexible printed circuit (FPC) was completed. The method exhibited sensitive signal characteristics, accurately sensed the material interface, and provided a clear criterion for identifying the removal process of multilayer materials by quantitative analysis of signal variation, which provides an innovative scheme for laser intelligent manufacturing of multilayer heterogeneous materials.

Method of solving single-event upset for heterogeneous dual field programmable logic gate array for infrared remote sensing camera in orbit

On-orbit reconstruction is a hotspot technology in the field of space infrared remote sensing cameras technology. Since the space infrared remote sensing cameras perform detection work under the space radiation environment, the core part of its image processing unit, which is a static random-access memory type field programmable logic gate array (FPGA), is susceptible to the impact of high-energy particles, especially during single-event upset events. The occurrence of point-like granular noise in remote sensing images will affect the normal imaging detection performance of the system, and even lead to abnormal timing of infrared detectors in severe cases, thereby affecting the normal operation of infrared remote sensing cameras. Aiming at the reliability requirements of the normal operation of space infrared remote sensing cameras in the space radiation environment, we propose a modular architecture of heterogeneous dual FPGA for XilinxVirtex-5 series FPGA, which carries out periodic refresh, reconstruction, and uploading of Virtex-5 series FPGA through antifuse FPGA. The antifuse FPGA periodically refreshes and reconstructs the Virtex-5 series FPGA from a one-time programmable read-only memory and injects the program into the program storage NOR flash device, and periodically refreshes and reconstructs the Virtex-5 series FPGA from NOR flash. This method can refresh and reconstruct the space infrared remote sensing camera in orbit. The in-orbit flight data verification shows that this method can effectively solve the impact of single-particle turnover event and improve the reliability of the infrared remote sensing camera in orbit operation.

A Survey on FPGA Cybersecurity Design Strategies

This article presents a critical literature review on the security aspects of field-programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. The article also pays special attention to emerging system-on-chip (SoC) FPGA devices that incorporate a hard processing system (HPS) on the same die as the FPGA logic. While this incorporation reduces the need for vulnerable external signals, the HPS in SoC FPGA devices adds a level of complexity that is not present for stand-alone FPGA devices. This added complexity necessarily hands over the task of securing the device to developers. Even with standard security features in place, the HPS might still have unhindered access to the FPGA logic. A single software flaw could open up a breach that might allow an attacker to extract the FPGA’s configuration data. A robust cybersecurity strategy is thus required for developers. As such, this work aims to provide the groundwork to build a solid threat-based cybersecurity design strategy that is specially adapted to SoC FPGA devices.

SPAD-Based LiDAR With Real-Time Accuracy Calibration and Laser Power Regulation

This brief reports a light detection and range (LiDAR) imager which incorporates an image sensor based on a single-photon avalanche diode (SPAD) with the resolution of 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\times }$ </tex-math></inline-formula> 32, a VCSEL-based laser emission system with the same resolution as image sensor as well as the pixel spacing, and a field programmable logic gate array (FPGA) used to realize the calibration algorithm and control the working time of the LiDAR imager. A gating high-voltage driver circuit drives the image sensor to reduce background noise interference and realize real-time accuracy calibration for the time-to-digital converter (TDC) with the resolution of 200 ps. The common-cathode driver circuit with the narrow pulse, adaptive frequency and power regulation drives different channels of VCSEL based on the time-division multiplexing method to improve the signal-to-noise ratio and reduce power consumption of the LiDAR imager. The LiDAR imager based on the proposed circuit architecture and calibration algorithm can achieve depth imaging up to 10 m revealing a repeatability error of 10 cm at 10 frames/s.

An FPGA-based trigger system for CSHINE

A trigger system of the general function was designed using the commercial module of CAEN V2495 for heavy-ion nuclear reaction experiments at Fermi energies. The system was applied and verified on the compact spectrometer for heavy IoN experiment (CSHINE). Based on the field-programmable logic gate array technology of the command register access and remote computer control operation, trigger functions can be flexibly configured according to experimental physical goals. Using the trigger system on CSHINE, we conducted a beam experiment at 25 MeV/u $$^{86}\textrm{Kr}+ ^{124}\textrm{Sn}$$ on the Radioactive Ion Beam Line 1 in Lanzhou, China. The online results demonstrated that the trigger system worked normally and correctly. This system can be extended to other experiments as well.

Development of a Signal Processing Software for Scintillation Detectors and Implementation on an FPGA for Fast Sensing

An open-source code RadSigPro 1.0 has been developed and used for fast processing of nanosecond-long pulses from scintillation detectors. This processing includes pulse height distribution (PHD), pulse shape discrimination (PSD), and time of flight (TOF). The code has been implemented onto the programmable logic design of a field programmable gate array (FPGA) design for on-the-fly processing of neutron and gamma-ray pulses. A weighted average of the percent difference of the results for RadSigPro 1.0 implemented on a CPU and a FPGA logic design is calculated. This shows a 0% difference for the PHD data sets, a 0.458% and 0.344% difference for the designated gamma detector and neutron detector PSD data sets, respectively, and a 0% difference for the TOF data set. When the FPGA logic design is applied and simulated, it computed the total and tail pulse areas within 5 ns of the arrival of the final data point used for accumulation and also captured the pulse height value within 2 ns of the arrival of the pulse’s maximum data point.

Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks

Field-programmable gate arrays (FPGAs) deployed on commercial cloud services are increasingly gaining popularity due to the cost and compute benefits offered by them. Recent studies have discovered security threats than can be launched remotely on FPGAs that share the logic fabric between trusted and untrusted parties, posing a danger to designs deployed on cloud FPGAs. With remote power analysis (RPA) attacks, an attacker aims to deduce secret information present on a remote FPGA by deploying an on-chip sensor on the FPGA logic fabric. Information captured with the on-chip sensor is transferred off the chip for analysis and existing on-chip sensors demand a significant amount of bandwidth for this task as a result of their wider output bit width. However, attackers are often left with the only option of using a covert communication channel and the bandwidth of such channels is generally limited. This paper proposes a novel area-efficient on-chip power sensor named PPWM that integrates a logic design outputting a pulse whose width is modulated by the power consumption of the FPGA. This pulse is used to clear a flip-flop selectively and asynchronously, and the single-bit output of the flip-flop is used to perform an RPA attack. This paper demonstrates the possibility of successfully recovering a 128-bit Advanced Encryption Standard (AES) key within 16,000 power traces while consuming just 25% of the bandwidth when compared to the state of the art. Moreover, this paper assesses the threat posed by the proposed PPWM to remote FPGAs including those that are deployed on cloud services.

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

To address some of the challenges of asynchronous design, we propose a new, decomposable asynchronous logic block architecture based on our TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> programmable threshold cell, and we use it to implement common threshold functions found in asynchronous, null convention logic circuits. At a minimum, programmable gate arrays require a programmable logic cell that can implement a complete set of logic. It is well known that a NAND function forms a complete set of logic, and in null convention logic, the TH12 and TH22 threshold cells are used to form a basic two-input NAND function. The TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell is capable of performing both TH12 and TH22 operations, so it too forms a complete set of logic. In this paper, we present our eight-transistor mask-programmable gate array logic cell, 16-transistor field-programmable gate array logic cell, and new decomposable field-programmable gate array logic block architecture, all based on the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell and suitable for implementing null convention logic asynchronous functions. To minimize the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell area for both TH12 and TH22 modes, we designed a layout with common Euler paths and no diffusion breaks for both modes. The highly compact nature of the TH<inline-formula> <tex-math notation="LaTeX">$x2$ </tex-math></inline-formula> threshold cell&#x2013;along with the symmetry of the mask- and field-programmable gate array logic cells&#x2013;made it an ideal candidate for an asynchronous field-programmable logic block structure. This paper is part of an ongoing project, and it only addresses the programmable logic block architecture, not a complete FPGA fabric.

Four-Channel Buck-Type LED Driver with Automatic Current Sharing and Soft Switching

A buck-type LED driver together with automatic current sharing and high step-down voltage conversion ratio but without complex control is proposed. The proposed LED driver can not only achieve zero voltage switching (ZVS) turn-on by adding only one resonant coupled inductor, which resonates with parasitic capacitors of active switches, but also can obtain lower voltage gain and better conversion efficiency. In this paper, the operating principles and design considerations of the proposed converter are discussed in detail. In addition, the number of LED strings can be extended to more than four channels. Finally, the theoretical analysis and performance of the proposed LED driver are verified by simulations and experiments using a field-programmable logic gate array (FPGA) named EP3C5E144C8N as a circuit control kernel.

FPGA-based multi-channel thermocouple temperature measurement system

Aiming at the high and low temperature test requirements of spacecraft before being sent into space, this paper designs and implements a multi-channel thermocouple temperature measurement system based on FPGA.The system adopts thermocouple as temperature sensor, and ADT7310 is used as thermocouple cold junction temperature compensation, which solves the problem of thermocouple cold junction compensation better.The front end adopts AD7193, a 24-bit analog-to-digital converter with low noise, multi-channel and low power consumption, to amplify and A/D convert the signal at measuring junction of thermocouple.The control core is a field programmable logic gate array FPGA, which can better solve the problem of parallel processing of multi-channel temperature signals. At the same time, it uses the transposition method of the thermocouple standard graduation table, the interpolation look-up table algorithm and the cold junction compensation reverse look-up table algorithm, which is effective The temperature measurement accuracy of each channel is improved.The experimental results show that the system can be connected to 24 K-type or T-type thermocouple sensors, the measurement range can reach -200°C∼220°C (73.15K∼493.15K), and the relative error is less than ±0.3%F.S.

Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance

The flexibility of field-programmable gate arrays (FPGAs) is attributed to the reconfigurability of their basic logic elements (BLEs). Traditionally, the BLEs are comprised of one or more lookup tables (LUTs) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> inputs, that are designed to implement Boolean functions of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n$ </tex-math></inline-formula> or fewer inputs. In an attempt to reduce the area and power consumption that comes from using LUTs, a number of complex LUT architectures have been reported. Although most of the proposed complex LUT architectures have resulted in reduced area and power, this has always been at cost of the decreased performance. This article proposes a new FPGA architecture, called threshold logic FPGA (TLFPGA), which results in significant improvement in performance, power, and area (PPA). TLFPGA is comprised of a combination of LUTs and a new type of BLE referred to as a threshold logic cell (TLC) (Muroga, 1987). Although TLCs implement a relatively small subset of Boolean functions known as threshold functions (Muroga, 1987), they require far fewer registers and multiplexers than an LUT, and are also significantly faster. This article describes the architecture of the TLFPGA and a technology mapping algorithm tailored for a TLFGA. On average, TLFPGA designs use 18% fewer registers and multiplexers, which improves the collective area of BLEs by approximately 16%, power by 14%, and performance by 5%. The improvements have been demonstrated in both 40 and 28 nm technologies for ISCAS-85 circuits as well as practical circuits, using industry-standard flows. The improvements were also demonstrated using a layout of the architecture.

Remote reconfiguration of FPGA-based wireless sensor nodes for flexible Internet of Things☆

Recently, sensor nodes in Wireless Sensor Networks (WSNs) have been using Field Programmable Gate Arrays (FPGA) for high-speed, low-power processing and reconfigurability. Reconfigurability enables adaptation of functionality and performance to changing requirements. This paper presents an efficient architecture for full remote reconfiguration of FPGA-based wireless sensors. The novelty of the work includes the ability to wirelessly upload new configuration bitstreams to remote sensor nodes using a protocol developed to provide full remote access to the flash memory of the sensor nodes. Results show that the FPGA can be remotely reconfigured in 1.35 s using a bitstream stored in the flash memory. The proposed scheme uses negligible amount of FPGA logic and does not require a dedicated microcontroller or softcore processor. It can help develop truly flexible IoT, where the FPGAs on thousands of sensor nodes can be reprogrammed or new configuration bitstreams uploaded without requiring physical access to the nodes.

A Large-Range Steering Optical Phased Array Chip and High-Speed Controlling System

The optical phased array (OPA) chip is becoming the core component of all-solid-state lidars. In order to realize the wide-angle range beam scanning and rapid control of OPA-based solid-state lidars, we design and fabricate a 64-channel silicon-based OPA chip based on thermo-optical modulation. In accordance with the optical phase control characteristics of the multichannel thermo-optic OPA chip, we propose a parallel random access memory (RAM) array technique to realize high-speed phase control for the OPA chip and build the hardware system with a field-programmable logic gate array (FPGA). This system is used to test the main performance indicators of the OPA chip and realizes the high-speed scanning control of the wide-angle range of the OPA output beam. The test results show that the OPA chip we designed can achieve fast beam scanning within a large angle range between &#x2212;32.5&#x00B0; and &#x002B;32.5&#x00B0;, and the chip has high working reliability. Combined with the control system we build, it can meet the high-speed radar scanning requirements of all-solid-state lidars. This work lays a good foundation for the subsequential development of our thermo-optical and electrooptic OPA all-solid-state lidar prototypes.

FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit

Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs.

Non-blocking programmable delay line with minimal dead time and tens of picoseconds jitter

We report a non-blocking high-resolution digital delay line based on an asynchronous circuit design. Field-programmable gate array logic primitives were used as a source of delay and optimally arranged using combinatorial optimization. This approach allows for an efficient trade-off of the resolution and a delay range together with a minimized dead time operation. We demonstrate the method by implementing the delay line adjustable from 23ns up to 1635ns with a resolution of 10ps. We present a detailed experimental characterization of the device focusing on thermal instability, timing jitter, and pulse spreading, which represent three main issues of the asynchronous design. We found a linear dependence of the delay on the temperature with the slope of 0.2 ps K-1 per logic primitive. We measured the timing jitter of the delay to be in the range of 7-165ps, linearly increasing over the dynamic range of the delay. We reduced the effect of pulse spreading by introducing pulse shrinking circuits and reached the overall dead time of 4-22.5ns within the dynamic range of the delay. The presented non-blocking delay line finds usage in applications where the dead time minimization is crucial, and tens of picoseconds of excess jitter is acceptable, such as in many advanced photonic networks.

A Decoder – Look up Tables for FPGAs

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.