Field Programmable Gate Array Prototype Research Articles

Real-time field-programmable gate array-based closed-loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia.

The open-loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real-time field-programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC-specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open-loop DCN-DBS or closed-loop DCN-DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real-time computation, was used for closed-loop DCN-DBS system. Closed-loop DCN-DBS was triggered only when symptomatic muscle EMG was detected in a real-time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed-loop DCN-DBS was more effective than an open-loop paradigm as it reduced the frequency of DBS. Our real-time FPGA-based DCN-DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

High-performance architecture for real-time high-definition short-wave infrared streaming video processing and its field programmable gate array prototype

High-performance architecture for real-time high-definition short-wave infrared streaming video processing and its field programmable gate array prototype

Python-Based Circuit Design for Fundamental Building Blocks of Spiking Neural Network

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the X variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips.

A VLSI Digital Circuit Platform for Performing Deterministic Stochastic Computing in the Time Dimension Using Fraction Operations on Rational Numbers

Stochastic computing (SC) is a method of expressing values in streams of random bits and performing computation with bitwise operations on the streams. Recently, it was found that SC can be conducted on deterministic bitstreams where a numerical value is represented uniformly by sections of 1s and 0s. This leads to deterministic SC, where the computing result can be 100% accurate. However, at the current stage, its circuit implementation has not reached the level of practicality. Moreover, the expressible values for operands are theoretically limited. An all-digital frequency synthesizer, time-average-frequency direct period synthesis (TAF-DPS), is proposed here as a hardware platform for performing deterministic SC in the time dimension. The TAF-DPS is used as a rational-number-to-time converter (RNTC), transforming a rational number into an electrical waveform. Waveforms of unique frequencies and duty cycles are then generated according to the operand values. Instead of digital bitwise operations, each computation is carried out in the time regime on waveforms. Hence, it can be regarded as an “analog-like” logical operation. This RNTC-based time-domain operation opens up a subfield of SC: rational number stochastic computing (RN-SC). In RN-SC, fraction computation can be executed with logic gates, and the result is 100% accurate. The enabling factor is the improvement in resource utilization since the time dimension is exploited more efficiently. With this extra resource of time, expansion of the scope of SC is expected. In this article, the working principle is elucidated, and the circuit is discussed. Furthermore, a field-programmable gate array (FPGA) prototype is created to validate this platform for SC. The aim of this work is to create a practical tool for broadening the use of SC.

DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture

To improve the performance and power efficiency of various algorithms in specific applications, reconfigurable architecture has become an effective choice in academia and industry. However, due to the slow context updates and the insufficient flexibility, the existing reconfigurable architectures suffer from performance bottlenecks. Therefore, this paper proposed a dynamic reconfiguration mechanism applied to dual-mode programmable reconfigurable array architecture. This mechanism adopts Huffman-like coding and mask addressing, and through the H-tree transmission network, it can transmit the reconfiguration instruction/context to a specific processing element or processing element cluster in unicast, multicast, or broadcast modes within a clock cycle and shut down unnecessary processing elements or processing element clusters according to the current configuration. Meanwhile, a homogeneous reconfigurable array is designed to verify the correctness and effectiveness of the proposed dynamic reconfiguration mechanism. In this array, the processing element supports both instruction flow and data flow modes. Finally, the proposed work is implemented in register transfer level synthesis and a field-programmable gate array prototype, and its performance is verified using high-efficiency video coding algorithm. The results show that the proposed reconfiguration mechanism can effectively improve the hardware resource utilization and reconfiguration efficiency, it also can achieve the performance breakthrough of the reconfigurable architecture.

An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks

This article proposes an uninterrupted processing technique for the convolutional neural network (CNN) accelerator. It primarily allows the CNN accelerator to simultaneously perform both processing element (PE) operation and data fetching that reduces its latency and enhances the achievable throughput. Corresponding to the suggested technique, this work also presents a low latency VLSI-architecture of the CNN accelerator using the new random access line-buffer (RALB)-based design of PE array. Subsequently, the proposed CNN-accelerator architecture has been further optimized by reusing the local data in PE array, incurring better energy conservation. Our CNN accelerator has been hardware implemented on Zynq-UltraScale + MPSoC-ZCU102 FPGA board, and it operates at a maximum clock frequency of 340 MHz, consuming 4.11 W of total power. In addition, the suggested CNN accelerator with 864 PEs delivers a peak throughput of 587.52 GOPs and an adequate energy efficiency of 142.95 GOPs/W. Comparison of aforementioned implementation results with the literature has shown that our CNN accelerator delivers 33.42% higher throughput and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.24\times $ </tex-math></inline-formula> better energy efficiency than the state-of-the-art work. Eventually, the field-programmable gate array (FPGA) prototype of the proposed CNN accelerator has been functionally validated using the real-world test setup for the detection of object from input image, using the GoogLeNet neural network.

Real-time post-processing for physical-layer secure key distribution in fiber networks

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double-threshold quantization, information reconciliation (IR) with Bose–Chaudhuri–Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.

Using Non-Autonomous Chaotic Clocks to Drive CPA-Resistant AES Cryptographic Chips

In this brief, we provide further evidence on the robustness of the chaotic clocking technique for driving a Correlation Power Analysis (CPA) resistant cryptographic chip running the Advanced Encryption Standard (AES). In particular, we explore the use of non-autonomous chaotic oscillators to improve the chip’s timing and power performance. We show that using this type of oscillator significantly reduces the performance degradation associated with switching from a normal periodic clock to a chaotic clock while remaining robust against side channel attacks. Simulations and experimental results using a Field Programmable Gate Array (FPGA) prototype are reported as a proof of concept.

Real-time FPGA prototyping of a 15GBaud SP-16QAM coherent optical receiver with optimal interpolating for clock recovery and equalization.

We demonstrate a real-time coherent optical receiver based on a single field programmable gate array (FPGA) chip. To strike the balance between the performance and hardware resources, we use a clock recovery scheme using the optimal interpolation (OI). The performance and complexity of the OI-based scheme and the traditional schemes are compared and discussed via offline digital signal processing. And a real-time 15GBaud single-polarization 16QAM transmission experiment under different received optical power using the FPGA-based receiver is carried out to demonstrate the overall performance of different clock recovery and equalization schemes. The result proves that, compared to the traditional scheme with a cubic interpolator and a 7-tap equalizer, the optimal interpolator significantly lowers the utilization of LUT, CARRY8, and DSP48 by 35%, 50%, and 11%, respectively, and can work properly under a received optical power of -40dBm.

A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System

In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

High quality hypergraph partitioning for logic emulation

Dividing a large-scale design into parts for hardware prototyping and emulation is very important for integrated circuit design flow. In this paper, we present a suite of algorithms to solve the partitioning problem in general field programmable gate arrays (FPGAs) prototyping and hardware emulation. Our k-way hypergraph partitioner is based on a multi-level framework and its performance is similar to the well-known partitioners hMetis (Karypis et al., 1999) and KaHyPar (Akhremtsev et al., 2017). Based on this framework, we take up some algorithms which solve partitioning problems with varying objectives and constraints extracted from logic emulation scenarios. These objectives and constraints take FPGA resources, interconnection resources, flip-flops, and clock domains into account, which are all important factors in FPGA prototyping and hardware emulation. We test our algorithms using ISPD98 benchmarks and several industry cases. The experimental results show that our algorithms are efficient and effective in solving different partitioning problems.

A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages

To improve the performance of SRAM in caches under near-threshold voltages, several timing speculation techniques, such as the cross-sensing SRAM (CS-SRAM), are proposed. Meanwhile, for a given process, voltage, and temperature (PVT) condition, CS-SRAM has an optimal bitline discharging time (TBL) to achieve the lowest average access latency. However, existing timing speculation caches do not track the variations of different PVT conditions to adjust the access timing to the optimal TBL point, on which the system possesses the lowest average memory access time. In this article, we propose a design of CS-SRAM-based L1 caches with a PVT autotracking mechanism, namely TS-PULP, which adjusts both the TBL and the frequency of the system clock to the optimal points. To quantify the improvement of our approach, a cycle-accurate RTL model of CS-SRAM and a field-programmable gate array (FPGA) prototype of the proposed L1 caches with the open-source system on chip (SoC) platform PULP have also been implemented. According to the evaluation results from RTL simulations and the FPGA prototype, the proposed caches can achieve a similar performance (over 80%) of the original standard cell memory (SCM)-based PULP design under TSMC 28 nm 0.5 V and 25 °C with only about 30% chip area. In addition, we introduced the figure of merit (FOM) of million instructions per second (MIPS), area, and energy (MAE) to comprehensively evaluate different approaches. The proposed scheme, TS-PULP, achieves the best FOM of MAE among four architectures (PULP with SCM, PULP with SRAM, TS-cache, and TS-PULP) with different cache sizes.

317 Gb/in2 Recording Areal Density on Strontium Ferrite Tape

The recording performance of a new prototype magnetic tape based on perpendicularly oriented strontium ferrite particles is investigated using a 29 nm wide tunneling magnetoresistive reader. At a linear density of 702 kbpi, a post-detection byte-error rate (BER) of 2.8e−2 is demonstrated based on measured recording data and a software read channel. The read channel uses a 64-state implementation of an extended version of a data-dependent noise-predictive maximum-likelihood detection scheme that tracks the first- and second-order statistics of the data-dependent noise. At the demonstrated post-detection BER, a post-error-correction-coding BER of less than 1e−20 can be achieved using an iterative decoding architecture. To facilitate aggressive track-density scaling, we made multiple advances in the area of track following. First, we developed a new timing-based servo pattern and implemented a novel quad channel averaging scheme. Second, we developed a new field programmable gate array prototyping platform to enable the implementation of quad channel averaging. Third, we enhanced our low disturbance tape transport with a pair of 20 mm diameter air bearing tape guides and a prototype track-following actuator. Fourth, we developed a novel low friction tape head and, finally, we designed a set of tape speed optimized track-following controllers using the model-based $H_{\infty }$ design framework. Combining these technologies, we achieved a position error signal (PES) characterized by a standard deviation ≤ 3.18 nm over a tape speed range of 1.2–4.1 m/s. This magnitude of PES in combination with a 29 nm wide reader enables reliable recording at a track width of 56.2 nm corresponding to a track density of 451.9 ktpi, for an equivalent areal density of 317.3 Gb/in2.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

An FPGA-Based Neuron Activity Extraction Unit for a Wireless Neural Interface

As computational and functional brain model development are solely dependent upon the data acquired from the neural interface, this device plays a vital role in both prosthetic developments and neurological experiments. A wireless neural interface is preferred over a traditional wired one because it can maximize the comfort of the subject and ensure the freedom of movement while implemented. This paper describes the field programmable gate array (FPGA) prototype design of a low-power multichannel neuron activity extraction unit suitable for a wireless neural interface. To achieve the low-power requirement, we proposed a novel neural signal extraction algorithm which can provide an up to 6000X transmission rate reduction considering the input signal. Consequently, this technique offers at least 2X power reduction compared to the state-of-the-art systems. We implemented this scheme in Xilinx Zynq-7000 FPGA, which can be used as an intermediate transition towards the application specific integrated circuit (ASIC) design for on-chip neural signal processing. The proposed FPGA prototype offers reconfigurable computability, which means the model can be modified and verified according to prerequisites before the final ASIC design. This prototype consists of a signal filtering unit and a signal extraction unit which can be used either as stand-alone units or combined as a complete system. Our proposed scheme also provides a provision to work as a single-channel or a scalable multichannel interface based on user’s demands. We collected practical neural signals from rat brains and validated the efficacy of the implemented system using in-silico signal processing.

Intellino: Processor for Embedded Artificial Intelligence

The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose the intellino, a processor for embedded artificial intelligence. Intellino ensures low power operation based on optimized AI algorithms and reduces the workload of the system core through the hardware implementation of a neural network. In addition, intellino’s dedicated protocol helps the embedded system to enhance the performance. We measure intellino performance, achieving over 95% accuracy, and verify our proposal with an field programmable gate array (FPGA) prototyping.

Real-time secure optical OFDM transmission with chaotic data encryption

Offline digital signal processing is generally applied in secure optical orthogonal frequency division multiplexing (OFDM) transmission, however the real-time secure optical OFDM transmission is necessary to evaluate the security and transmission performances. Thus a real-time secure optical OFDM transmission with chaotic data encryption is developed to demonstrate the high-speed data transmission with high-level physical-layer confidentiality, where field-programmable gate array (FPGA) boards are employed for the real-time encryption and decryption of optical OFDM signals, along with pipeline analog-to-digital and digital-to-analog converters. The physical-layer security enhancement is attributed to hyper digital chaos, providing a huge key space of 1045. As a proof of concept, the real-time encrypted 16-QAM optical OFDM signal transmission at 435 Mb/s is successfully demonstrated over 22 km standard single-mode fiber (SSMF), without any degradation in transmission performance. The proposed FPGA prototype can be a good candidate for the practical implementation of secure data transmission in OFDM passive optical network.

Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques

There has been a growing trend in recent years to outsource various aspects of the semiconductor design and manufacturing flow to different parties spread across the globe. Such outsourcing increases the risk of adversaries adding malicious logic, referred to as hardware Trojans, to the original design. The increased complexity of modern microprocessors increases the difficulty in detecting hardware Trojans at early stages of design and manufacturing. Therefore, there is a need for run-time detection techniques to capture Trojans that escape detection at these stages. In this paper, we introduce a machine learning-based run-time hardware Trojan detection method for microprocessor cores. This approach uses changepoint-based anomaly detection algorithm to detect the activation of Trojans that introduce abnormal patterns in the data streams obtained from performance counters. It does not modify the original microprocessor design to integrate on-chip monitoring sensors. We evaluate our method by detecting the activation of Trojans that cause denial-of-service, the degradation of system performance, and change in functionality of a microprocessor core. Results obtained using the OpenSPARC T1 core and an field-programmable gate array (FPGA) prototyping framework show that the Trojan activation is detected with a true positive rate of above 99% and a false positive rate of 0% for most of the implemented Trojans.