Real-time post-processing for physical-layer secure key distribution in fiber networks

Abstract

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double-threshold quantization, information reconciliation (IR) with Bose–Chaudhuri–Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.