Using Non-Autonomous Chaotic Clocks to Drive CPA-Resistant AES Cryptographic Chips

Abstract

In this brief, we provide further evidence on the robustness of the chaotic clocking technique for driving a Correlation Power Analysis (CPA) resistant cryptographic chip running the Advanced Encryption Standard (AES). In particular, we explore the use of non-autonomous chaotic oscillators to improve the chip’s timing and power performance. We show that using this type of oscillator significantly reduces the performance degradation associated with switching from a normal periodic clock to a chaotic clock while remaining robust against side channel attacks. Simulations and experimental results using a Field Programmable Gate Array (FPGA) prototype are reported as a proof of concept.