Field Programmable Gate Array Platform Research Articles

An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications

This paper proposes a novel method to improve the performance and reduce the implementation design complexity of the angular domain cyclostationary feature detection (CFD). This method implements Orthogonal Frequency Division Multiplexing (OFDM) signal detection for cognitive radio applications. The originality of this work is based on using a selective sampling process for the OFDM signal detection by using only samples related to the cyclic prefix (CP). Using only the first NCP (CP length) angles of the angular domain cyclic autocorrelation function and eliminating the remaining angles has significantly improved the detector sensitivity. Results from Matlab simulations revealed that the proposed method reaches a detection probability of 100% at an SNR (signal-to-noise ratio) equal to −16 dB in the case of an additive white Gaussian noise (AWGN) channel. Moreover, the proposed method outperforms the other CFD methods with a performance range up to 5 dB. The proposed algorithm is coded using the VHDL language and implemented with the minimum of counters and comparators on Field-programmable gate array (FPGA) platform without using multipliers and DSP blocks. The proposed design requires a lesser power, logic and memory bits by 5.95, 60.96 and 87.5%, respectively, compared to the conventional angular domain CFD design. The proposed hardware architecture can be more efficient for spectrum sensing in many communication systems, such as LTE-Advanced and the L-band Digital Aeronautical Communication System (LDACS).

Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform

The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.

Analog/Digital Multiplierless Implementations for Nullcline-Characteristics-Based Piecewise Linear Hindmarsh-Rose Neuron Model

Multipliers are essential in implementing nonlinear neuron models, but they take huge implementation costs. Many multiplierless fitting schemes have been proposed to simplify the implementation of nonlinearities in neuron models. To optimize these schemes, this paper presents a nullcline-characteristics- based piecewise linear (NC-PWL) fitting scheme for multiplierless implementations of Hindmarsh-Rose (HR) neuron model. This NC-PWL fitting scheme uses as few line segments as possible to approximate the critical nonlinearity characteristics of the local nullclines. A NC-PWL HR neuron model that reproduces diverse firing patterns of the original one is successfully established. Using off-the-shelf low-cost components, an analog multiplierless circuit is designed for this fitting model and welded on print circuit board (PCB). Meanwhile, by logical shift method, a digital multiplierless circuit with low resource consumption is developed for this fitting model on field-programmable gate array (FPGA) platform. Experimental results of the analog and digital multiplierless hardware implementations verify the numerical simulations and show the simplicity and feasibility of the presented fitting scheme.

SoC FPGA-Based Rapid Prototyping of Compressed, Secured and Wireless Image Transmission for Wildlife Surveillance System

Wildlife plays an important role in balancing the earth’s ecosystem. Today, many species of wildlife are threatened with extinction. Images are important input data for wildlife surveillance technology,whichallowsreal situations in the field to be observed and analysed. This project proposed a wireless transmission systemof compressedandsecured imagesusing the SoCFPGA platformfor improving the existing systemin terms of image data collection. Image compression ensuredthat the proposed system wasefficient in terms of data processing, transmission and storage. Image data encryption aimed at ensuring that the security of the transmitted image data would not be hijacked by poachers or non-authorities and ultimately this system wouldtransmit compressed and secured images wirelessly to provide real-time data. The prototype usedLabVIEW 2017 software and NI myRIO (as image transmitter) and a computer (as image receiver) hardware. This platform has been utilisedfor the development of the architectural design of a compression system using the discrete cosine transform (DCT) method, the development of an encryption system using the advanced encryption standards (AES) method and wireless transmission using Wi-Fi. The implementation of DCT on the field-programmable gate array (FPGA) platform allowedthe imagesto be compressed by an average of 44% to shortenthe time used in the transmission process. The AES method guaranteeddata security with images that can only be viewedwhenusing the correct password. Combining both the DCT and AES methods, the rapid prototyping of the wireless transmission of compressed and secured images for a wildlife surveillance system equippedwith a motion sensor and a camera was developed to detect motion, capture imagesand transmit three (3) different image resolutions atdistances of up to 60m.

Hardware implementation of neural network-based engine model using FPGA

This paper implements an artificial neural network (ANN)-based engine model using the Field Programmable Gate Array (FPGA). The developed (ANN)-based engine model will be used to estimate the engine gas emissions to mitigate the harmful effects of these emissions on human health. Getting reliable and robust FPGA-based ANNs implementations depends on the optimal choice of activation function that will provide minimal area occupation on FPGA. This study introduces, implements, and investigates FPGA-based ANN-based engine models using five different activation functions. These implemented engine models were described using MATLAB/Simulink and hardware description language coder and carried out by Spartan -3E-500.CP132 FPGA platform from Xilinx. The performance of the implemented engine models was investigated in terms of area-efficient implementation and the regression values (R) to build a robust ANN-based engine model.

Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking

Both modern datacenter and embedded Field Programmable Gate Arrays (FPGAs) provide great opportunities for high-performance and high-energy-efficiency computing. With the growing public availability of FPGAs from major cloud service providers such as AWS, Alibaba, and Nimbix, as well as uniform hardware accelerator development tools (such as Xilinx Vitis and Intel oneAPI) for software programmers, hardware and software developers can now easily access FPGA platforms. However, it is nontrivial to develop efficient FPGA accelerators, especially for software programmers who use high-level synthesis (HLS).The major goal of this article is to figure out how to efficiently access the memory system of modern datacenter and embedded FPGAs in HLS-based accelerator designs. This is especially important for memory-bound applications; for example, a naive accelerator design only utilizes less than 5% of the available off-chip memory bandwidth. To achieve our goal, we first identify a comprehensive set of factors that affect the memory bandwidth, including (1) the clock frequency of the accelerator design, (2) the number of concurrent memory access ports, (3) the data width of each port, (4) the maximum burst access length for each port, and (5) the size of consecutive data accesses. Then, we carefully design a set of HLS-based microbenchmarks to quantitatively evaluate the performance of the memory systems of datacenter FPGAs (Xilinx Alveo U200 and U280) and embedded FPGA (Xilinx ZCU104) when changing those affecting factors, and we provide insights into efficient memory access in HLS-based accelerator designs. Comparing between the typically used soft and hardened memory systems, respectively, found on datacenter and embedded FPGAs, we further summarize their unique features and discuss the effective approaches to leverage these systems. To demonstrate the usefulness of our insights, we also conduct two case studies to accelerate the widely used K-nearest neighbors (KNN) and sparse matrix-vector multiplication (SpMV) algorithms on datacenter FPGAs with a soft (and thus more flexible) memory system. Compared to the baseline designs, optimized designs leveraging our insights achieve about\( 3.5\times \)and\( 8.5\times \)speedups for the KNN and SpMV accelerators. Our final optimized KNN and SpMV designs on a Xilinx Alveo U200 FPGA fully utilize its off-chip memory bandwidth, and achieve about\( 5.6\times \)and\( 3.4\times \)speedups over the 24-core CPU implementations.

Optimizing the Deep Neural Networks by Layer-Wise Refined Pruning and the Acceleration on FPGA.

To accelerate the practical applications of artificial intelligence, this paper proposes a high efficient layer-wise refined pruning method for deep neural networks at the software level and accelerates the inference process at the hardware level on a field-programmable gate array (FPGA). The refined pruning operation is based on the channel-wise importance indexes of each layer and the layer-wise input sparsity of convolutional layers. The method utilizes the characteristics of the native networks without introducing any extra workloads to the training phase. In addition, the operation is easy to be extended to various state-of-the-art deep neural networks. The effectiveness of the method is verified on ResNet architecture and VGG networks in terms of dataset CIFAR10, CIFAR100, and ImageNet100. Experimental results show that in terms of ResNet50 on CIFAR10 and ResNet101 on CIFAR100, more than 85% of parameters and Floating-Point Operations are pruned with only 0.35% and 0.40% accuracy loss, respectively. As for the VGG network, 87.05% of parameters and 75.78% of Floating-Point Operations are pruned with only 0.74% accuracy loss for VGG13BN on CIFAR10. Furthermore, we accelerate the networks at the hardware level on the FPGA platform by utilizing the tool Vitis AI. For two threads mode in FPGA, the throughput/fps of the pruned VGG13BN and ResNet101 achieves 151.99 fps and 124.31 fps, respectively, and the pruned networks achieve about 4.3× and 1.8× speed up for VGG13BN and ResNet101, respectively, compared with the original networks on FPGA.

FPGA-Based CNN for Real-Time UAV Tracking and Detection

Neural networks (NNs) are now being extensively utilized in various artificial intelligence platforms specifically in the area of image classification and real-time object tracking. We propose a novel design to address the problem of real-time unmanned aerial vehicle (UAV) monitoring and detection using a Zynq UltraScale FPGA-based convolutional neural network (CNN). The biggest challenge while implementing real-time algorithms on FPGAs is the limited DSP hardware resources available on FPGA platforms. Our proposed design overcomes the challenge of autonomous real-time UAV detection and tracking using a Xilinx’s Zynq UltraScale XCZU9EG system on a chip (SoC) platform. Our proposed design explores and provides a solution for overcoming the challenge of limited floating-point resources while maintaining real-time performance. The solution consists of two modules: UAV tracking module and neural network–based UAV detection module. The tracking module uses our novel background-differencing algorithm, while the UAV detection is based on a modified CNN algorithm, designed to give the maximum field-programmable gate array (FPGA) performance. These two modules are designed to complement each other and enabled simultaneously to provide an enhanced real-time UAV detection for any given video input. The proposed system has been tested on real-life flying UAVs, achieving an accuracy of 82%, running at the full frame rate of the input camera for both tracking and neural network (NN) detection, achieving similar performance than an equivalent deep learning processor unit (DPU) with UltraScale FPGA-based HD video and tracking implementation but with lower resource utilization as shown by our results.

FPGA-Based Reconfigurable Convolutional Neural Network Accelerator Using Sparse and Convolutional Optimization

Nowadays, the data flow architecture is considered as a general solution for the acceleration of a deep neural network (DNN) because of its higher parallelism. However, the conventional DNN accelerator offers only a restricted flexibility for diverse network models. In order to overcome this, a reconfigurable convolutional neural network (RCNN) accelerator, i.e., one of the DNN, is required to be developed over the field-programmable gate array (FPGA) platform. In this paper, the sparse optimization of weight (SOW) and convolutional optimization (CO) are proposed to improve the performances of the RCNN accelerator. The combination of SOW and CO is used to optimize the feature map and weight sizes of the RCNN accelerator; therefore, the hardware resources consumed by this RCNN are minimized in FPGA. The performances of RCNN-SOW-CO are analyzed by means of feature map size, weight size, sparseness of the input feature map (IFM), weight parameter proportion, block random access memory (BRAM), digital signal processing (DSP) elements, look-up tables (LUTs), slices, delay, power, and accuracy. An existing architectures OIDSCNN, LP-CNN, and DPR-NN are used to justify efficiency of the RCNN-SOW-CO. The LUT of RCNN-SOW-CO with Alexnet designed in the Zynq-7020 is 5150, which is less than the OIDSCNN and DPR-NN.

Low-area and high-speed hardware architectures of LBlock cipher for Internet of Things image encryption

Security is becoming an essential field of research as network technology is changing at a rapid pace. Digital images are transmitted in many modes of communication. This transmission must be secure, particularly in applications that demand a high level of security, such as military applications, surveillance, radars, and biometrics. Two hardware solutions of the lightweight block cipher LBlock are provided to secure image data. These proposed architectures are implemented on a Xilinx field programmable gate arrays (FPGA) platform, and the implementation results are compared with existing state-of-the-art designs. The proposed designs took 56 and 64 slices operating at a frequency of 492.441 and 681.663 MHz, respectively, on a Virtex-5 FPGA platform. In addition, the proposed round-based and pipelined designs showed improvement in hardware efficiency over state-of-the-art designs. The proposed hardware architectures are capable of securing different sizes of gray-scale and RGB color images. These hardware solutions were verified by different analyses, including correlation coefficient, mean square error (MSE), peak signal-to-noise ratio (PSNR), histogram, entropy, number of pixel changing rate (NPCR), and unified average changing intensity (UACI). The existing solutions were compared with correlation coefficients, NPCR, UACI, MSE, PSNR, and entropy values and provide better solutions than the state-of-the-art designs.

Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs

Static random access memory (SRAM) based field-programmable gate array (FPGA) is currently facing challenges of high leakage power and limited capacity. Replacing SRAM in FPGA with emerging nonvolatile memory (NVM) has become an effective way to solve this issue. While enjoying the advantages of NVM in power consumption and integration, nonvolatile FPGA platform is also plagued by lifetime problem. Among all components, block random access memory (BRAM) has the severest endurance problem. The state-of-the-art wear leveling strategies for NVM-based BRAMs rely heavily on static analysis. However, the static analysis would not be accurate enough for application with multiple runtime working patterns. In this article, we propose a pattern-aware wear leveling mechanism. It can improve lifetime through adaptive reconfiguration without static analysis. Evaluation shows that our mechanism can achieve 120% higher lifetime improvement with 4% performance overhead than existing performance-aware wear leveling strategy (Huai et al., 2019).

IEEE 802.1AS Clock Synchronization Performance Evaluation of an Integrated Wired–Wireless TSN Architecture

Industrial control systems present numerous challenges from the communication systems perspective: clock synchronization, deterministic behavior, low latency, high reliability, flexibility, and scalability. These challenges are mostly solved with standard technologies over Ethernet, e.g., time-sensitive networking (TSN). As a research trend, it is expected that TSN will converge with wireless, leading to the Wireless TSN paradigm. Also, Wireless TSN is expected to be integrated with Ethernet TSN to create large-scale wired–wireless (Hybrid) TSN networks. The first step toward Hybrid TSN is the distribution of the clock reference from the wired to the wireless domain. In this article, we leverage existing Ethernet TSN and wireless technologies implementations (Wi-Fi and w-SHARP) and present two hardware architectures specifically engineered to enable the clock synchronization distribution among the network domains. The hardware architectures have been implemented over a system-on-chip field-programmable gate array platform. We demonstrate through several experiments that the implementation is able to fulfill the synchronization performance required by TSN.

Gesture Recognition System Using 24 GHz FMCW Radar Sensor Realized on Real-Time Edge Computing Platform

Affected by the global epidemic, non-contact unmanned control system provides people with safe human-computer interaction (HCI). This paper presents a radar hand gesture recognition system based on real-time edge computing platform. The system uses a low-cost 24 GHz commercial low bandwidth frequency modulated continuous wave (FMCW) radar as the detection source. For real-time gesture recognition, the background echo of radar is fitted by the exponential weighted average method which can reduce the hardware resource consumption when implementing on field programmable gate array (FPGA). A novel extracted feature named range-Doppler matrix focus (RDMF) is designed to reduce the data dimension and preserve the useful information. 3-D CNN + LSTM encoder classification framework is used to classify the features. A data set of 3200 samples for the basic 8 gestures and 1600 samples for the additional 4 gestures is designed and collected for training and testing the classification framework. The results show that the average accuracy of 3-D CNN + LSTM encoder on training and testing data set of 12 gesture classification exceeds 97.9%. The model size of this network is nearly 390 kB. In order to compress the size for recognition on edge-computing platform, a simplified framework for sending one antenna’s RDMF to the LSTM encoder is proposed. The model size is reduced to 20 kB, and the average accuracy of the simplified framework on basic 8 gestures is 95.9%. We deploy this gesture recognition framework on the FPGA platform to speed up computing.

FPGA-Based BNN Architecture in Time Domain with Low Storage and Power Consumption

With the increasing demand for convolutional neural networks (CNNs) in many edge computing scenarios and resource-limited settings, researchers have made efforts to apply lightweight neural networks on hardware platforms. While binarized neural networks (BNNs) perform excellently in such tasks, many implementations still face challenges such as an imbalance between accuracy and computational complexity, as well as the requirement for low power and storage consumption. This paper first proposes a novel binary convolution structure based on the time domain to reduce resource and power consumption for the convolution process. Furthermore, through the joint design of binary convolution, batch normalization, and activation function in the time domain, we propose a full-BNN model and hardware architecture (Model I), which keeps the values of all intermediate results as binary (1 bit) to reduce storage requirements by 75%. At the same time, we propose a mixed-precision BNN structure (model II) based on the sensitivity of different layers of the network to the calculation accuracy; that is, the layer sensitive to the classification result uses fixed-point data, and the other layers use binary data in the time domain. This can achieve a balance between accuracy and computing resources. Lastly, we take the MNIST dataset as an example to test the above two models on the field-programmable gate array (FPGA) platform. The results show that the two models can be used as neural network acceleration units with low storage requirements and low power consumption for classification tasks under the condition that the accuracy decline is small. The joint design method in the time domain may further inspire other computing architectures. In addition, the design of Model II has certain reference significance for the design of more complex classification tasks.

Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.

A CASE STUDY OF VARIOUS WIRELESS NETWORK SIMULATION TOOLS

4G is the fastest developing system in the history of mobile communication networks. Network connectivity is paramount for all kinds of big enterprises. 4G not only provides super-fast connectivity to millions of users, but can also act as an enterprise network connectivity enabler and it has inherent advantages such as higher bandwidth, low latency, higher spectrum efficiency along with backward compatibility and future proofing. The design of the 4G based Long Term Evolution physical network provides the required flexibility for optimization during the development phase. In this paper LTE Network related supporting simulation tools is presented to demonstrate the need of Hardware co-simulation of the LTE system. After the feasibility analysis, the importance of the model is to be ported Field Programmable Gate Array platform is examined in survey in detail with the supporting inferences along with the comparison of different wireless network simulators suitable for LTE.

Efficient Low-Complexity Turbo-Hadamard Code in UAV Anti-Jamming Communications

Unmanned aerial vehicle (UAV) systems undergo a period of rapid development in both civil and military scenarios. A major challenge in the malicious jamming environment is to guarantee the reliability of UAV communications links. Frequency hopping (FH) is one of the most commonly used means of combatting the influence brought about by jamming. In this paper, we integrate low-rate codes into an anti-jamming FH communications system, and propose an efficient and low-complexity turbo-Hadamard code scheme. Tail-biting is applied to design the component convolutional-Hadamard codes, and a corresponding decode algorithm is used for implementation in the UAV hardware platform. Numerical simulation results demonstrate that the anti-jamming performance of this method is improved as compared with conventional concatenated codes. Finally, we compare the complexity and transmission efficiency of the proposed algorithm with the algorithms implemented on the field programmable gate array (FPGA) platform in detail.

The Comparison, Analysis and Circuit Implementation of the Chaotic Systems

A four-dimensional chaotic system with complex dynamical properties is constructed. The complexity of the system was evaluated by equilibrium point, Lyapunov exponential spectrum and bifurcation model. The coexistence of Lyapunov exponential spectrum and bifurcation model proves the coexistence of attractors. [Formula: see text] and SE complexity algorithms are used to compare and analyze the corresponding complexity characteristics of the system, and the most complex integer-order system is obtained. In addition, the circuit to switch between different chaotic attractors is novel. In particular, more complex parameters are selected for the fractional-order chaotic system through the analysis of parameter complexity, and the rich dynamics of the system are analyzed. Experimental results based on Field-Programmable Gate Array (FPGA) platform verify the feasibility of the system. Finally, the most complex integer-order system is compared with its corresponding fractional-order system in image encryption, so that the fractional-order system has a better application prospect.

Design of Convolutional Neural Network Based on FPGA

Recently with the rapid development of artificial intelligence AI, various deep learning algorithms represented by Convolutional Neural Networks (CNN) have been widely utilized in various fields, showing their unique advantages; especially in Skin Cancer (SC) imaging Neural networks (NN) are methods for performing machine learning (ML) and reside in what's called deep learning (DL). DL refers to the utilization of multiple layers during a neural network to perform the training and classification of data. The Convolutional Neural Networks (CNNs), a kind of neural network and a prominent machine learning algorithm go through multiple phases before they get implemented in hardware to perform particular tasks for a specific application. State-of-the-art CNNs are computationally intensive, yet their parallel and modular nature make platforms like Field Programmable Gate Arrays (FPGAs) compatible with the acceleration process. The objective of this paper is to implement a hardware architecture capable of running on an FPGA platform of a convolutional neural network CNN, for that, a study was made by describing the operation of the concerned modules, we detail them then we propose a hardware architecture with RTL scheme for each of these modules using the software ISE (Xilinx). The main objective is to show the efficiency of such a realization compared to a GPU based execution. An experimental study is accomplished for the PH2 database set of benchmark images. The proposed FPGA-based CNN design gives competitive results and shows well its efficiency.

Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

This paper presents four highly efficient hardware architectures for Deblocking Filter (DBF) which can be used in High-Efficiency Video Coding (HEVC) encoder or decoder. Mixed pipelined and block processing techniques are used in these architectures to achieve high throughput while consuming minimum possible area. In these proposed architectures, the coding tree unit with 64 × 64 blocks of pixels in a frame are processed in the form of 32 × 32 blocks of pixels. Once the deblocking filtering process completes, these pixels will be stored in block memory via output buffer. Experimental results on Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms demonstrate that the proposed hardware architecture has a throughput improvement of 69% to 83% at the expense of slightly increased gate count compared to the previously known architectures of DBF. With 180 nm technology library, the fastest architecture out of the four achieves a throughput of 162 FPS (Frames per second) at an operating frequency of 250 MHz.