Real-time Field Programmable Gate Array Research Articles

Real-time field-programmable gate array-based closed-loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia.

The open-loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real-time field-programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC-specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits. We implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open-loop DCN-DBS or closed-loop DCN-DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real-time computation, was used for closed-loop DCN-DBS system. Closed-loop DCN-DBS was triggered only when symptomatic muscle EMG was detected in a real-time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed-loop DCN-DBS was more effective than an open-loop paradigm as it reduced the frequency of DBS. Our real-time FPGA-based DCN-DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

Cyber-Secure Global Energy Equalization in DC Microgrid Clusters Under Data Manipulation Attacks

Cyber physical microgrids (MGs) are vulnerable to data manipulation attacks which can lead to significant imbalance in the MG. For instance, data manipulations by cyber adversaries may cause to higher loading of batteries with low state-of-charge. This will lead to degradation of the cycle-life of batteries unless timely intervention is done for malware detection. Therefore, a cyber-secure global energy equalisation of battery energy storage systems in multiple interconnected direct current (DC) MG clusters is proposed in this article for efficient utilisation of batteries. Cyber security is achieved in the framework through the proposed multi-level detection and mitigation paradigm aided by event generators. Firstly, it is the maiden attempt to propose and design a secure global energy equalisation framework for MG clusters. Secondly, the proposed event generators enable segregated defensive actions for leader and follower nodes in the network. This is unlike previously reported works wherein the defense mechanism has been generalised for every node. Further, the results indicate that the proposed event generators help in maintaining continuity of power to critical loads in the system. Extensive time-domain simulations are performed in MATLAB/Simulink under various practical scenarios of ad- versarial intrusions. Controller hardware-in-loop tests employing real-time digital simulator (RTDS) and field programmable gate array (FPGA) based WAVECT Controller are also performed for real-time validation of the proposed technique. Finally, for testing scalability of the algorithm, it is extended to 20 DC-DC converters.

Position sensitive detector based non-contact vibration measurement with laser triangulation method utilizing Gabor Transform for noise reduction

Measurement of vibration without having contact with the target is crucial for many applications. However, real time vibration signals are frequently mixed with various levels of dynamic noises. In this research, a non-contact type vibration measurement system based on laser triangulation method is proposed by using a PSD (Position sensitive detector) and here a single axis Brüel and Kjaer piezoelectric accelerometer is used to validate the experimental results. The primary goal of this measurement system is to develop a Gabor Transform based signal denoising technique, in order to eliminate noise from the real-time vibration data. Furthermore, PSD platform vibration, which might cause unanticipated inaccuracies in the detected vibration data, has also been eliminated by utilizing a self-vibration compensation approach using an ADXL-345 three-axis accelerometer. The self-vibration compensated vibration measurement technique has been designed using an NI (national instruments) cRIO (CompactRIO) 9074 real-time FPGA (field programmable gate array) based embedded controller. Consequently, a Gabor Transform and Expansion-based Signal Processing Technique is designed using NI cRIO-9074 real time platform to reduce external noise from the self-vibration compensated vibration data. It has been observed that the implementation of Gabor Transform has improved the performance of the system in term of enhancing the SNR (Signal-to-noise ratio).

Real-Time FPGA Simulation of High-Voltage Silicon Carbide MOSFETs

This article presents a real-time field-programmable gate array (FPGA)-based dynamic model of high-voltage and high-current silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) half-bridge power modules. The dynamic switching model utilizes the Shichman and Hodges equations using voltage-dependent nonlinear device capacitances and module electrical parameters to obtain an accurate dynamic model of the device switching transients. The key device states gate-source voltage, drain current, and drain-source voltage are modeled and discretized using forward Euler discrete integration method. Analysis of synthesizing the discrete-time model into real-time FPGA-based system with real-time data output from the on-board digital-to-analog converter is presented in detail. The model is utilized in modeling a 320-kW, medium-voltage dc/dc dual-active bridge converter and verified using dynamic experimental results from a 3.3-kV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> half-bridge power module. It has been shown that the presented discrete-time dynamic switching model accurately describes the turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> switching transients of the SiC power module at various voltage and current levels. Such models are useful for rapid and cost effective design and prototyping of SiC-based power electronic systems by defining key design and operating parameters, such as deadtime, switching frequency, and switching losses.

Real-time post-processing for physical-layer secure key distribution in fiber networks

Physical-layer secure key distribution (PLSKD) in fiber networks provides robust security and full compatibility with current fiber infrastructure. The post-processing is generally required to improve the key consistency, security, and randomness in PLSKD. However, offline digital signal processing was generally adopted in the previous PLSKD schemes, while the real-time high-speed post-processing is necessary towards the practical PLSKD applications. In this paper, a real-time pipeline post-processing is designed and demonstrated using field-programmable gate array (FPGA) boards. A complete set of post-processing is applied, including double-threshold quantization, information reconciliation (IR) with Bose–Chaudhuri–Hocquenghem code, and privacy amplification (PA) with SM3 hash algorithm. The system architecture is detailed by combining all these processing steps, where the trade-offs for the post-processing scheme are analyzed. We also assess the performance of post-processing implementation on FPGA in terms of throughput and hardware resource utilization. The throughput of post-processing is optimized by pipeline design approach with the parallel processing capability of FPGA, where the maximum data throughputs are 50, 57.1, and 332.5 Mb/s for the quantization, IR, and PA, respectively. On the FPGA platform, the final key rate is up to 12.2 Mb/s. The proposed real-time post-processing FPGA prototype is a good candidate for the practical application of PLSKD in fiber networks.

Applying edge artificial intelligence to closed-loop real time control and monitoring of laser based battery pack welding

The manufacturing of battery packs plays an essential role in e-mobility. In this context, laser welding of batteries has taken a considerable momentum in recent years as it can quickly adapt to different form factors and battery arrangements which is crucial for short runs and on-demand manufacturing. In this paper, we present an assisted battery pack welding system applying a novel sensor fusion strategy. The presented work introduces a multi-camera solution combining a camera in the visual range and an infrared camera in a compact scanner head that applies graphics processing unit acceleration for image processing and real-time field programmable gate array processing for process control. In order to acquire accurate temperature measurements, the infrared camera has been characterized and calibrated for the temperature ranges of the welding process. In addition, we propose a method for image space coordinate transformation based on affine transformations used to transform the coordinates of the detected battery joints into different image spaces to adapt to the welding process in real time. A single shot multibox detector Mobilenet-v2 neural network has been retrained with custom images to detect and classify a set of battery pack types allowing the extraction of the battery cell joint coordinates using image processing, which enables the application of real-time corrections to the laser aiming system and a closed-loop laser power control. Finally, we present some battery welding results using different welding strategies on the described system.

Real-time FPGA prototyping of a 15GBaud SP-16QAM coherent optical receiver with optimal interpolating for clock recovery and equalization.

We demonstrate a real-time coherent optical receiver based on a single field programmable gate array (FPGA) chip. To strike the balance between the performance and hardware resources, we use a clock recovery scheme using the optimal interpolation (OI). The performance and complexity of the OI-based scheme and the traditional schemes are compared and discussed via offline digital signal processing. And a real-time 15GBaud single-polarization 16QAM transmission experiment under different received optical power using the FPGA-based receiver is carried out to demonstrate the overall performance of different clock recovery and equalization schemes. The result proves that, compared to the traditional scheme with a cubic interpolator and a 7-tap equalizer, the optimal interpolator significantly lowers the utilization of LUT, CARRY8, and DSP48 by 35%, 50%, and 11%, respectively, and can work properly under a received optical power of -40dBm.

RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment

This article presents a real-time FPGA (field-programmable gate array) based fog node architecture with a remote dynamically reconfigurable application plane. The proposed FPGA-based fog node exhibits high architectural flexibility to enable fog analytics dynamic redeployment, which is critical for adapting to application dynamicity and prolonging product lifespan. The proposed fog node architecture is implemented in an FPGA without GPP (general-purpose processor) and tested experimentally in the NetFPGA development board with a case study on anomaly detection analytics that is commonly used in IoT (Internet-of-Things) time-series monitoring applications. The Windowed Gaussian and KNN CAD implementations in FPGA have been benchmarked with the NAB (Numenta Anomaly Benchmark) environment for performance assessment. Significantly, the latency and throughput improvement for the KNN CAD in FPGA implementation over software is approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$61\times $ </tex-math></inline-formula> , while Windowed Gaussian is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42\times $ </tex-math></inline-formula> and thus, both analytics attained <1 ms real-time responsiveness. The implemented FPGA-based Windowed Gaussian and KNN CAD anomaly detection analytics has the respective energy efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.06~\mu \text{J}$ </tex-math></inline-formula> and 0.12 mJ for each detection. In short, the proposed FPGA-based fog node exhibits high energy efficiency, low latency, and high throughput in network packet and data analytics processing for greener fog networks and real-time IoT applications.

A Crest Factor Reduction Technique for LTE Signals with Target Relaxation in Power Amplifier Linearization.

The signal conditioning treatment to achieve good relation of power with radio-frequency (RF) conversion in conventional transceiver systems require precise baseband models. A developed framework is built to provide a demonstration of the modeling figures of merit with orthogonal frequency division multiplexing (OFDM) support under signal conditioning and transmission restrictions to waveforms with high peak to average power ratio (PAPR) in practical applications. Therefore, peak and average power levels have to be limited to correct high PAPR for a better suited correction power from the amplifier that can lead to compression or clipping in the signal of interest. This work presents an alternative joint crest factor reduction (CFR) algorithm to correct the performance of PAPR. A real-time field-programmable gate array (FPGA) testbed is developed to characterize and measure the behavior of an amplifier using a single-carrier 64–QAM OFDM based on long-term evolution (LTE) downlink at GHz as stimulus, across wide modulation bandwidths. The results demonstrate that the CFR accuracy capabilities for the signal conditioning show a reliable clipping reduction to give a smooth version of the clipping signal and provide a factor of correction for the unwanted out-of-band emission validated according to the adjacent channel power ratio (ACPR), PAPR, peak power, complementary cumulative distribution function (CCDF), and error vector magnitude (EVM) figures of merit.

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

Hardware-in-the-loop real-time validation of fuel cell electric vehicle power system based on multi-stack fuel cell construction

This paper proposed a Fuel Cell Electric Vehicle (FCEV) power system model which was validated by Hardware-in-the-Loop (HIL) real-time emulation. Multi-stack Fuel Cell (MFC) system was used to increase the system redundancy. Nickel-metal Hydride (NiMH) battery pack (BAT) was selected as the secondary energy source. Dual-input single-output Boost converters were connected with MFC system to satisfy the voltage requirement of DC bus. Bi-directional Buck-Boost converter was connected with BAT and then both discharging and charging modes were controlled. Close loop control strategies were developed for converters to assure their stabilities. Rule-based Energy Management Strategy (REMS) was proposed to distribute the required power among Proton Membrane Exchange Fuel Cells (PEMFCs) and BAT. The proposed model was evaluated by HIL real-time emulation, using the Supplemental Federal Test Procedure US06 (SFTP-US06) driving cycle. MicroLabBox, in which real-time processor and Field Programmable Gate Array (FPGA) were embedded, was selected as the HIL real-time validation platform. The MFC system, BAT model, REMS and low-level controllers were executed by real-time processor while the converter general models were built in FPGA. According to the results, the proposed model and method effectively driven MFC system operating in high efficiency region and successfully kept BAT State of Charge (SOC) in the desired range.

FPGA Realization of ANFIS Controller Using a Proposed Digital Design

The design and realization of Adaptive Neuro-Fuzzy Inference System (ANFIS) controller based on Field Programmable Gate Array (FPGA) is presented in this paper. The controller intended to control the temperature of medical oven. A novel design of digital ANFIS is presented here for the implementation process. Different controllers are designed and their results are compared using MATLAB program to show the ANFIS superiority. The designed controllers tested for cell cultures application at 37.5. A reduction is made for the designed digital ANFIS due to the used FPGA limitations. The reduced design minimizes the utilized slices from 366% to 3% and LUTs from 364% to 3%. The reduced design reached an optimum size for this controller to utilize a smallest memory size. A real-time FPGA implementation of the proposed digital ANFIS have been done and verified through Xilinx ISE 14.6 using the VHDL language. The VHDL code for the controller is produced, aggregated and downloaded on the FPGA Spartan 3A/AN FPGA kit. A comparison between the simulation and implementation results is made. The matching between these results proves the effectiveness and robustness of the proposed digital ANFIS and the excellent performance of the FPGA based controller.

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm

Harris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.

Field programmable Gate Array based Real Time Object Tracking using Partial Least Square Analysis

In this paper, we proposed an object tracking algorithm in real time implementation of moving object tracking system using Field programmable gate array (FPGA). Object tracking is considered as a binary classification problem and one of the approaches to this problem is that to extract appropriate features from the appearance of the object based on partial least square (PLS) analysis method, which is a low dimension reduction technique in the subspace. In this method, the adaptive appearance model integrated with PLS analysis is used for continuous update of the appearance change of the target over time. For robust and efficient tracking, particle filtering is used in between every two consecutive frames of the video. This has implemented using Cadence and Virtuoso software integrated environment with MATLAB. The experimental results are performed on challenging video sequences to show the performance of the proposed tracking algorithm using FPGA in real time.

FPGA-based infrared image deblurring using angular position of IR detector

The motion of the object or the infrared (IR) imaging system during the integration time causes blurring of the IR image. This study covers real-time field programmable gate array (FPGA)-based deblurring for IR detectors, and an inertial measurement unit (IMU) was used to quantify the blur caused by the IR detector movement. Point spread function for each pixel was calculated using the angular position data of the IR detector obtained from IMU. Both spatially invariant and spatially variant blur cases can be modeled for the IR detector motion. After the quantification, the spatially invariant-type blur was eliminated using a Wiener filter-based deblurring algorithm. Deblurring algorithm was implemented in the Xilinx system generator environment directly using FPGA IP cores. The simulation results in the Xilinx system generator environment indicate that the proposed image deblurring method is real-time applicable, and it reduces the processing time of a single frame to 4 ms. For the implementation of 2D-fast Fourier transform design in FPGA using the corner turn matrix method, memory management is the most critical factor influencing the speed. The real-time deblurring solution given herein has the potential to be used in IR cameras on the moving platforms to increase the performance and robustness in systems such as object tracking and visual navigation.

An Improved Adaptive Control Strategy in Grid-Tied PV System With Active Power Filter for Power Quality Enhancement

This article investigates the power quality enhancement of a grid-tied photovoltaic (PV) distribution system by employing a fuzzy logic proportional-integrator-derivative multiple complex coefficient filter multiple second-order generalized integrator frequency-locked loop (FLPID-MCCF-MSOGI-FLL) hybrid control scheme based shunt active power filter. The MSOGI-FLL reference current generation strategy is implemented to mitigate the current harmonics by extracting the fundamental constituents (FCs) from the nonlinear load currents, whereas an MCCF is employed to separate the FC from the distorted grid voltages and eliminates the voltage harmonics during extremely polluted grid voltage condition. The main objective of using FLPID is to maintain the stable power between dc and ac sides by regulating the dc-link voltage constant under transient conditions. To track the maximum power from the PV panel under varying environmental condition, the particle swarm optimization based perturb and observe technique is used in this article. The comparative analysis is analyzed to check the effectiveness of the proposed hybrid control scheme with existing and adaptive control techniques in respect of power quality, better dc offset rejection, better FC and frequency extraction, and grid synchronization. The system with the proposed control scheme is simulated on MATLAB/Simulink and validated in a real-time field-programmable gate array platform under different test scenarios. In conclusion, the harmonic content of grid currents and voltages is found well within the IEEE-519 standard limits.

The development, design and characterisation of a scale model Horizontal Axis Tidal Turbine for dynamic load quantification

The paper describes the development and characterisation of three 0.9 m diameter lab-scale Horizontal Axis Tidal Turbines. The blade development process has been outlined and was used to generate a design specification. Each turbine houses instrumentation to measure rotor thrust, torque and blade root bending moments on each blade, in both ‘flapwise’ and ‘edgewise’ directions. A permanent magnet synchronous machine and encoder are integrated to allow for servo-control of the turbine as well as to provide position and rotational velocity measurements, resulting in three turbines that can be individually controlled using speed or torque control. Analogue signals are captured via a real-time operating system and field programmable gate array hardware architecture facilitating sample rates of up to 2 kHz. Results from testing the pilot turbine at three differing facilities during the development process are presented. Here good agreement, less than 7% variation, was found when comparing the testing undertaken at various flume and tow tank facilities. Lastly, the findings of a test campaign to characterise the performance of each of the three turbines are presented. Very good agreement in non-dimensional values for each of the three manufactured turbines was found.

Low-Power Dynamic Object Detection and Classification With Freely Moving Event Cameras.

We present the first purely event-based, energy-efficient approach for dynamic object detection and categorization with a freely moving event camera. Compared to traditional cameras, event-based object recognition systems are considerably behind in terms of accuracy and algorithmic maturity. To this end, this paper presents an event-based feature extraction method devised by accumulating local activity across the image frame and then applying principal component analysis (PCA) to the normalized neighborhood region. Subsequently, we propose a backtracking-free k-d tree mechanism for efficient feature matching by taking advantage of the low-dimensionality of the feature representation. Additionally, the proposed k-d tree mechanism allows for feature selection to obtain a lower-dimensional object representation when hardware resources are limited to implement PCA. Consequently, the proposed system can be realized on a field-programmable gate array (FPGA) device leading to high performance over resource ratio. The proposed system is tested on real-world event-based datasets for object categorization, showing superior classification performance compared to state-of-the-art algorithms. Additionally, we verified the real-time FPGA performance of the proposed object detection method, trained with limited data as opposed to deep learning methods, under a closed-loop aerial vehicle flight mode. We also compare the proposed object categorization framework to pre-trained convolutional neural networks using transfer learning and highlight the drawbacks of using frame-based sensors under dynamic camera motion. Finally, we provide critical insights about the feature extraction method and the classification parameters on the system performance, which aids in understanding the framework to suit various low-power (less than a few watts) application scenarios.

A real-time FPGA accelerated stream processing for hyperspectral image classification

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

Realization of real-time DSP for C-band PAM-4 transmission in inter-datacenter network.

We designed and realized real-time pulse amplitude modulation-4 (PAM-4) digital signal processing (DSP) including forward error correction (FEC) for a C-band inter-datacenter network. The PAM-4 DSP is intended to compensate for chromatic dispersion and provide dispersion tolerance. A decision feedback equalizer (DFE) and maximum likelihood sequence equalizer (MLSE) were employed for the dispersion compensation. A low-density parity check (LDPC) code was used to increase coding gain. The soft-decision Viterbi algorithm (SOVA) was adopted to provide probabilistic information to the LDPC code. For implementation in a real-time field programmable gate arrays (FPGAs), we employed fully parallelized structures. In the design, three LDPC cores were operated in parallel, and the equalizers were also operated with 128 PAM-4 symbols. With the DSP, we empirically proved the feasibility of 25 km transmission without error-floor sign, corresponding to a dispersion compensation capacity of 425 ps/nm. We confirmed 35 km ∼ 85 km error-free transmission for inter-datacenter network.