Field Programmable Gate Array Implementation Research Articles

LabPET II scanner performances improvement: Thermal stability control based on FPGA

The LabPET II detection module serves as the fundamental component within Positron Emission Tomography (PET) scanners designed for achieving ultra-high-resolution imaging of small to medium-sized animals as well as the human brain. To ensure peak performance, it is imperative that this module operates consistently at a stable temperature. In this paper, we present an automatic and real-time method to improve the thermal control of the scanner LabPET II by evacuating the heat to reduce the overall temperature and maintain the thermal stability of the system. Based on the Thermo-Electric Cooler (TEC) process, our method applies two numerical techniques, Computational Fluid Dynamics (CFD) and Heat Transfer Analysis (HTA). The Dirichlet Boundary Conditions (DBC) method is applied for the Application-Specific Integrated Circuit (ASIC) at 25∘ C. The real measurements confirm and validate the simulation results with the Finite Element Method (FEM) based on the software COMSOL Multiphysics™. Field-Programmable Gate Array (FPGA) implementation on the Development and Education (DE1) board is performed with comparative results study. The proposed method is both simple and practical, and ensures thermal stability at 35∘C for the duration of operation of the scanner, which has a complex structure.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor.

FPGA Implementation of a Phase Optimizer-Assisted PTS Scheme for PAPR Reduction in OFDM Systems

This article proposes a phase optimizer-assisted partial transmit sequence (PO-PTS) for minimizing PAPR values in OFDM systems. The novel PO-PTS scheme after validation, based on simulation results, is implemented using a Xilinx system generator on a field programmable gate array (FPGA). The phase optimizer (PO) module is employed to select optimal phase weighting factors to perform scaling with the data sequence in the PTS scheme. The computational complexity and the redundancy involved in producing the candidate signals are significantly reduced by the PO-PTS compared with the conventional PTS method. The proposed method reduces PAPR for a QPSK-OFDM signal by 56.16% compared to the original OFDM signal without compromising on the bit error rate (BER) performance. In addition, the performance of PO-PTS in terms of PAPR reduction for 32-QAM and 64-QAM modulated OFDM systems is also presented to justify the robustness of the proposed scheme. Moreover, when PO-PTS is implemented using FPGA, it uses only 1% of the hardware available in Virtex.

Small RCS targets detection based on pulse compression radar signal generator and processor

In the last two decades, field programmable gate arrays (FPGAs) have become the leading technology for implementing real time systems, specially radars. The most important advantage of FPGA is its parallel nature of executing complicated algorithms. As a result, the received data flow will be processed in a real time manner, which is suitable for radar applications. This paper attempts to show the design and the FPGA implementation of a binary phase-coded pulse compression radar signal generator and processor, that are intended to determine the ranges, and the speeds of targets with small radar cross-section area like drones. The system operating waveform is a bi-phase sequence, that is known to have the best known peak sidelobe level compared to compound Barker codes of the same length. In addition, the design incorporates a range sidelobes cancellation method to remove the time sidelobes in the matched filter output. Also, we are going to represent and investigate the FPGA implementing steps of the radar waveform generator and processor according to the required parameters. Finally, the implementation results of the proposed system will be represented.

Experimental Observation of Chaotic Attractors from the FPGA implementation of 3D Chaotic Systems

In recent years, researchers have designed and implemented chaotic oscillators using digital hardware elements to develop applications like secure communications and random number generation. Due to its programmability and low-cost characteristics, one of the most used digital devices to synthesize chaotic systems is the field-programmable gate array (FPGA), which is recommended for fast prototyping. In this manner, this paper shows the experimental observation of seven chaotic attractors that are simulated using the Verilog hardware description language, and implemented in an FPGA. The seven designs are Lorenz-type systems, which are designed from the discretization of their equations using the well-known Forward Euler method. The block description of the seven chaotic systems employs the fixed-point numerical format using 32 bit. The simulations of the chaotic systems using Matlab and Active-HDL software, along with the block diagrams of the designs, are presented. The final part of the work illustrates the experimental attractors on a Teledyne Lecroy oscilloscope, obtained by using an FPGA Cyclone II EP2C35F672C6 and a 16-bit digital-to-analog converter.

Echo state network implementation for chaotic time series prediction

The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new design of quadratic order b-splines and four integer multipliers. The FPGA implementation of the ESNN is applied to predict four chaotic time series associated to the Lorenz, Chua, Lü, and Rossler chaotic oscillators. The experimental results show that with 50 hidden neurons, the fixed-point arithmetic is good enough when using 15 or 16 bits in the fractional part: using more bits does not reduce the mean-squared error prediction. The neurons are limited to four inputs in the hidden layer to achieve a more efficient hardware implementation, guaranteeing a prediction of more than 10 steps ahead.

FPGA implementation of carrier-based PWM techniques for single-phase matrix converters

Field programmable gate arrays (FPGAs) stand out as a highly efficient and reliable digital solution to control power electronics converters. Direct single-to-single-phase matrix converters (SSMCs) are widely used in industrial and power system-related applications and are usually controlled using carrier-based PWM techniques. Existing literature studies on FPGA implementation of carrier-based PWM techniques for SSMC lack providing architectural design details and programming algorithms. Further, resource utilization/power consumption optimizations and analyses are not performed. To fill these research gaps, we propose a new FPGA-based design that is capable of employing the desired carrier-based PWM technique and synthesizing any output frequency. It also optimizes the FPGA resource utilization and power consumption and utilizes a novel approach to synchronize the generated triggering pulses with the source. A laboratory setup is built to experimentally test the proposed FPGA-based design, where results demonstrate the efficiency and reliability of the design.

Hardware architecture of Dillon’s APN permutation for different primitive polynomials

Cryptographically strong functions used as S-boxes in block cyphers are fundamental for the cypher’s security. Their representation as lookup tables is possible for functions of small dimension. For larger dimensions, this is infeasible, especially if resources are limited. An alternative is representing the function as a polynomial over a finite field, and constructing a circuit evaluating this polynomial. We study how the choice of primitive polynomial affects the efficiency of hardware implementations. We take Dillon’s permutation on 6 bits (the only known permutation in even dimension from the cryptographically optimal Almost Perfect Nonlinear functions) as a relevant example, and present hardware architectures, polynomial representations and hardware theoretical complexities for all primitive polynomials of degree six. To compare the efficiency, we report on results obtained from FPGA (Field Programmable Gate Array) implementations. To the best of our knowledge, no similar study has been given in the literature. We observe that using the primitive trinomial y6+y+1 reduces the number of 2-input XOR gates up to 11.7% and the number of XOR gates × Delay metrics up to 13.2% with respect to the worst-case implementation. Therefore, the choice of primitive polynomial can profoundly impact the efficiency of such an implementation, and should be carefully considered.

FPGA implementation of a robust DTC-SVM based Sliding Mode Flux Observer for a double star induction motor: Hardware in the loop validation

This paper presents an implementation of a robust Direct Torque Control (DTC)-Space Vector Modulation (SVM) strategy for a Double Star Induction Machine (DSIM) using a Field Programmable Gate Array (FPGA). The proposed control technique combines SVM and DTC strategies, incorporating the Sliding Mode Flux Observer (SMFO) to improve robustness and overcome the drawbacks of stator resistance variations. First, SVM is used to improve DTC performance by reducing torque and flux ripples generated with classical DTC strategies. Then, the SMFO is employed to estimate the mechanical speed and stator flux module, ensuring robustness in the face of stator resistance variations. A comparative study between conventional DTC, DTC-SVM, and DTC-SVM-SMFO is presented. Simulation tests of the three DTC strategies were conducted using Matlab/Simulink tools, demonstrating the robustness and high performance of the DSIM under DTC-SVM-SMFO. To further validate these results, the technique was implemented using Xilinx System Generator (XSG) on a parallel processing software environment, the FPGA Virtex 5. Hardware in the loop results confirms the effectiveness of the DSIM under the improved DTC-SVM-SMFO control strategy.

Method of creation of FPGA based implementation of artificial intelligence as a service

The subject of study in this article is the technologies of Field Programmable Gate Array (FPGA), methods, and tools for prototyping of hardware accelerators of Artificial Intelligence (AI) and providing it as a service. The goal is to reduce the efforts of creation and modification of FPGA implementation of Artificial Intelligent projects and provide such solutions as a service. Task: to analyze the possibilities of heterogeneous computing for the implementation of AI projects; analyze advanced FPGA technologies and accelerator cards that allow the organization of a service; analyze the languages, frameworks, and integrated environments for the creation of Artificial Intelligence projects for FPGA implementation; propose a technique for modifiable FPGA project prototyping to ensure a long period of compatibility with integrated environments and target devices; propose a technique for the prototyping of FPGA services with high performance to improve the efficiency of FPGA based AI projects; propose a sequence of optimization of neural networks for FPGA implementation; and provide an example of the practical implementation of the research results. According to the tasks, the following results were obtained. Analysis of the biggest companies and vendors of FPGA technology is performed. Existing heterogeneous technologies and potential non-electronic mediums for AI computations are discussed. FPGA accelerator cards with a large amount of High Bandwidth Memory (HBM) on the same chip package for implementation of AI projects are analyzed and compared. Languages, frameworks, and technologies as well as the capabilities of libraries and integrated environments for prototyping of FPGA projects for the AI applications are analyzed in detail. The sequence of prototyping of FPGA projects that are stable to changes in the environment is proposed. The sequence of prototyping of highly efficient pipelined projects for data processing is proposed. The steps of optimization of neural networks for FPGA implementation of AI applications are provided. An example of practical use of the results of research, including the use of sequences is provided. Conclusions. One of the main contributions of this research is the proposed method of creation of FPGA based implementation of AI projects in the form of services. Proposed sequence of neural network optimization for FPGA allows the reduction of the complexity of the initial program model by more than five times for hardware implementation depending on the required accuracy. The described solutions allow the construction of completely scalable and modifiable FPGA implementations of AI projects to provide it as a service.

An efficient design methodology to speed up the FPGA implementation of artificial neural networks

In this paper, we propose and formulate a C++ based training methodology for speeding up the implementation of an Artificial Neural Network (ANN) in a Field Programmable Gate Array (FPGA). The proposed ANN implementation methodology uses a custom C++ based program referred to as Neural Network Design Parameter Extraction (NNDPE) program developed using an open source library namely Fast Artificial Neural Network (FANN). The proposed C++ based NNDPE program reduces the time required to train and extract the design parameters of the ANN, such as the number of layers, the number of neurons in each layer, and the weights. The extracted ANN design parameters, custom hardware arithmetic units, and function-approximate activation functions are used to implement the ANN hardware architecture of a linear function on the Virtex-7 FPGA platform. The Vivado 2018.3 tool is used to simulate, synthesize, and implement the ANN-based linear function. It was concluded from the simulation that the ANN hardware implementation has high precision due to the usage of floating-point arithmetic operations compared to the ANN which uses fixed-point arithmetic operations. The ANN-implemented on the Virtex-7 FPGA operates at 150.76 MHz, which is approximately 11 to 18 times faster than the software implementation running on various CPU cores with operating frequencies ranging over 2.2 GHz to 4.70 GHz.

IEC61131-3 Instruction List Language Processor for FPGAs

This paper presents the architecture and field-programmable gate array (FPGA) implementation of a 32-bit central processing unit (CPU) dedicated to programmable logic controllers (PLCs). The CPU instruction set directly matches the instructions of the IEC 61131-3 standard Instruction List (IL) language. The designed IL processor is capable of handling 1-bit, 8-bit, 16-bit, and 32-bit data types. Apart from integer arithmetic operations, the IL processor also performs single precision floating-point operations included in the IEC 61131-3 IL language specification. It also directly performs instructions with a parenthesis modifier for all supported data types and facilitates the fast execution of a code containing Boolean expressions. This paper also presents the performance evaluation results of the developed IL processor. Although the IL processor executed the test algorithms substantially faster than industrial PLCs (e.g., Siemens S7-1200 and Fanux VersaMax), it turned out to be significantly slower than high-performance programmable automation controllers (PACs).

VLSI design and FPGA implementation of state-of-charge and state-of-health estimation for electric vehicle battery management systems

State of charge (SOC) and state of health (SOH) estimation is an important function in electric-vehicle (EV) battery-management systems (BMSs). SOC and SOH are the principal parameters for judging a battery’s state and critical for ensuring its safety and performance. In a conventional EV BMS, SOC and SOH estimation is performed on the master. However, owing to the increasing number of battery cells and computational cost of estimation algorithms, hardware-oriented processing for each single-battery module on the slave is being researched to reduce the master’s burden. Accordingly, this paper describes the hardware-optimized algorithm, VLSI design, and field-programmable gate array (FPGA) implementation verification results of an application-specific integrated circuit in a slave module to estimate SOC and SOH for multiple cells. We introduce an SOC and SOH estimation algorithm with 70% complexity reduction within a 2% error margin based on each cell’s voltage, current, and temperature and design a hardware block and logic circuit to implement the algorithm. An FPGA was utilized to verify the designed logic circuit, revealing a performance time of 0.65μs at 100 MHz. Finally, an FPGA testbed connected to a real battery and analog-front-end board was built to check the real-time performance through a graphical user interface.

Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder

For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder, decoding performance and area efficiency must be balanced. This paper adopts a layered decoder method to improve the area efficiency of the decoder. By parallel processing of three submatrices and storage reuse of node information, optimizing the matrix partitioning and processing order of the 50G-PON standard, the throughput of 1235 bps was reached under 100 MHz circuit frequency in field-programmable gate array (FPGA) implementation, and 9.864 Gbps was achieved based on Taiwan semiconductor manufacturing company (TSMC) 65 nm synthesis with 800 MHz circuit frequency in an area of 2.61 mm2 by proposing a mechanism of spare decision storage to avoid errors caused by quantization overflow of the decoder and using full verification to terminate decoding in advance to improve performance. Finally, at an input bit error rate (BER) of 2.3×10−2 (signal-to-noise ratio (SNR) of about 3.72 dB), the output BER was lower than 10−12, and the throughput area rate (TAR) also increased by 2 to 4 times compared with other papers. In conclusion, an area-efficient LDPC decoder without sacrificing decoding performance is made.

Peak Cancellation Method With IIR Filters and Its FPGA Implementation

To improve the efficiency of power amplifiers (PA) in communication transmitters, peak cancellation (PC) in the time domain is often implemented on a Field-programmable gate array (FPGA) to reduce the peak-to-average power ratio (PAPR) of the baseband signals. However, to reduce the out-of-band radiation, the existing techniques tend to use high-order finite impulse response (FIR) filters, which increases the input-to-output delay and resource consumption of FPGA. To address this issue, a PC method with the infinite impulse response (IIR) filter is proposed in this brief. The design criteria of the IIR filter for PC is given. The FPGA implementation scheme and resource optimization are discussed. To verify the performance of the proposed method, MATLAB simulation and FPGA implementation are made with a 5G NR signal. The comparison with the state-of-the-art PC methods shows that the proposed technique can reduce the total time delay greatly, with good PC performance and low resource consumption.

FPGA Implementation for Finite-Time and Fixed-Time Neurodynamic Algorithms in Constrained Optimization Problems

In this paper, two neurodynamic algorithms and the corresponding Field-Programmable-Gate-Array (FPGA) implementation scheme are presented, respectively. Firstly, based on Lagrange programming neural networks (LPNN) and sliding mode control technique, an algorithm with finite-time convergence and an algorithm with fixed-time convergence is proposed and used to solve constrained optimization problems. Then, the Update module, the Control module, the Gradient module, the finite-time processing (FTP) module, and the fixed-time processing (FxTP) module are designed to form an FPGA hardware implementation of neurodynamic optimization algorithms. The LPNN-based FPGA reconfigurable circuit framework can be structured by invoking the Update module, the Control module, and the Gradient module. The FTP module or the FxTP module can be called into the above framework to form the finite-time or fixed-time stable FPGA reconfiguration framework. Finally, the effectiveness and practicality of the proposed FPGA hardware implementation scheme is verified through example simulations implemented on the Vivado 2019.1 platform.

FPGA implementation for 44.2368-Gbit/s PAM8 signal transmission with pruned pre-equalization.

In this experiment, we demonstrated an intensity modulation and direct-detection (IM/DD) system based on a field-programmable gate array (FPGA). The PAM8 signals are successfully delivered at 44.2368 Gbit/s over a 45-km standard single-mode fiber (SSMF), satisfying the soft-decision forward error correction (SD-FEC) criterion of 2.4 × 10-2, and the net bit rate may reach 36.864 Gbit/s without the need of optical amplifiers. At the transmitter, we used a pruned pre-equalization algorithm to process the PAM8 signals, and the high-speed parallel PAM8 signals were processed at the receiver using 64 parallel constant modulus algorithm (CMA) and decision-directed least mean square (DD-LMS) equalizers. Additionally, we analyzed the bit error rate (BER) performance of the DD-LMS equalizer in FPGA simulation with various data lengths, both before and after equalization.

Power Function Algorithms Implemented in Microcontrollers and FPGAs

The exponential function ax is widespread in many fields of science. Its calculation is a complicated issue for Central Processing Units (CPUs) and Graphics Processing Units (GPUs), as well as for specialised Digital Signal Processing (DSP) processors, such as Intelligent Processor Units (IPUs), for the needs of neural networks. This article presents some simple and accurate exponential function calculation algorithms in half, single, and double precision that can be prototyped in Field-Programmable Gate Arrays (FPGAs). It should be noted that, for the approximation, the use of effective polynomials of the first degree was proposed in most cases. The characteristic feature of such algorithms is that they only contain fast ‘bithack’ operations (‘bit manipulation technique’) and Floating-Point (FP) addition, multiplication, and (if necessary) Fused Multiply-Add (FMA) operations. We published an article on algorithms for this class of function recently, but the focus was on the use of approximations of second-degree polynomials and higher, requiring two multiplications and two additions or more, which poses some complications in FPGA implementation. This article considers algorithms based on piecewise linear approximation, with one multiplication and one addition. Such algorithms of low complexity provide decent accuracy and speed, sufficient for practical applications such as accelerators for neural networks, power electronics, machine learning, computer vision, and intelligent robotic systems. These are FP-oriented algorithms; therefore, we briefly describe the characteristic parameters of such numbers.

Hardware-friendly tone-mapping operator design and implementation for real-time embedded vision applications

Tone-mapping is required to convert High Dynamic Range (HDR) images to Low Dynamic Range (LDR) images for viewing on standard displays. Most recent works in the domain include the efficient implementation of tone-mapping algorithms on Graphics Processing Units (GPUs) for throughput improvements. However, their downside is significantly high power consumption, making such solutions unsuitable for displays on embedded and general consumer electronic devices. In contrast, Field Programmable Gate Arrays (FPGAs) have demonstrated significant speedup on data-intensive image and video applications with a much lower power consumption than GPUs. This paper proposes a modular, scalable and resource-efficient FPGA implementation of a global Tone-Mapping Operator (TMO) based on histogram of the scene luminance and characteristics of the Human Visual System (HVS). Compared to GPU based implementation of a state-of-the-art TMO, our FPGA implementation achieved a higher throughput in the range of 2.5× to 4.5× with power savings of more than two orders of magnitude. Moreover, tonal quality of the proposed solution is better than the baseline TMO in approximately 80% of a dataset of 288 HDR images. The proposed solution also outperformed the state-of-the-art FPGA implementations of other TMOs in throughput, resource usage and scalability.