Small RCS targets detection based on pulse compression radar signal generator and processor

Abstract

In the last two decades, field programmable gate arrays (FPGAs) have become the leading technology for implementing real time systems, specially radars. The most important advantage of FPGA is its parallel nature of executing complicated algorithms. As a result, the received data flow will be processed in a real time manner, which is suitable for radar applications. This paper attempts to show the design and the FPGA implementation of a binary phase-coded pulse compression radar signal generator and processor, that are intended to determine the ranges, and the speeds of targets with small radar cross-section area like drones. The system operating waveform is a bi-phase sequence, that is known to have the best known peak sidelobe level compared to compound Barker codes of the same length. In addition, the design incorporates a range sidelobes cancellation method to remove the time sidelobes in the matched filter output. Also, we are going to represent and investigate the FPGA implementing steps of the radar waveform generator and processor according to the required parameters. Finally, the implementation results of the proposed system will be represented.