Field Programmable Gate Array Hardware Resources Research Articles

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA.

A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

Template-Based Adaptive Training Acceleration Framework for Deep Learning Algorithms

<p indent=0mm>Field-programmable gate array (FPGA) is usually used to accelerate the training phase of deep learning algorithms, but it usually requires a long development cycle and rich hardware design expertise for satisfied execution performance. In order to deal with this challenge, an adaptive acceleration framework for deep learning algorithm is proposed in this paper. We investigate the application scale, parallel scheduling strategy, resource usage and the scalability of functionality. With the CPU-FPGA heterogeneous acceleration template based technology, an adaptive model compiler is proposed to customize the accelerator based on the algorithm’s complexity and hardware resources available. The proposed hardware and software co-design framework can effectively adapt to different FPGA hardware resources and support the fast evolution of deep learning algorithms. Taking the graph neural network as an example, it can obtain 7~41x performance improvements compared to the general purpose CPU platform.

ЦИФРОВІ КОМПАРАТОРИ ЧАСТОТИ ТА ФАЗИ В СКЛАДІ СИСТЕМИ СТАБІЛІЗАЦІЇ ПОЛОЖЕННЯ РУХОМОЇ ПЛАТФОРМИ

Urgency of the research. A dual-range, four-quadrant position stabilization system (PSS) of a brushless direct current motor (BLDC) as a part of movable platform (MP), in which the power stage is based on a quasi-resonant pulse converter (QRPC), has the better speed and accuracy characteristics in comparison with hard-switching PWM-based converters. Target setting. The BLDC PSS can be built on the basis of the classic multi-loop control system (MLCS), or on the pulse-frequency (PF-) domain. In PF-domain the task of speed control is transformed into the frequency comparing and matching task, and the position control is transformed into the phasecomparing and matching between the reference signal and the feedback signal. The development of specialized digital blocks of a frequency comparator (FK) and a phase comparator (PC) to perform the above tasks is a non-trivial task. Actual scientific researches and issues analysis. The earliest solutions of the FC, which should be correctly called the ‘frequency detector’ (FD), were implemented mixed-signal (contained both analog and digital nodes) due to their usage in a high-frequency phase-locked loop (PLL) system. A full-featured FC consists of two counters, comparator, a FD block, control finite-state machine (FSM), and a specialized combinational circuit. Uninvestigated parts of general matters defining. Existing FC blocks do not return a quantitative relation between measured frequencies, which can be used to predict dynamics, and are insensitive to the detection of small misalignments between frequencies, that, in turn, creates instability of determining the frequencies equality state. Existing PC blocks are unstable when the frequency of one of the measured signals reaches the system clock frequency, and also do not take into account the edges incoming order of the measured signals. The research objective. The article is devoted to the study and development of the structure of pure-digital FC and PC blocks, which will eliminate the disadvantages of existing solutions and are oriented for integration into PSS with QRPC in the power stage and MLCS operates in a PF-domain. The statement of basic materials. A novel technical solutions is proposed, developed and tested for pure-digital blocks of the FC and PC built on the basis of the field-programmable gate array (FPGA) by means of the hardware description language (VHDL). They allow not only to measure the sign of the inequality of frequency and phase between two periodic signals, but also to obtain the difference numerical values between them. Conclusions. The installation of the FC and PC blocks into the BLDC PSS leads to a significant reducing of FPGA hardware resources utilization and to the high reliability and noise immunity of the MLCS through the unruptured (continiously) nature of the signals. Both the proposed blocks are novel and have eliminated the inherent disadvantages of the existing blocks of the FC and PC due to the installation of additional digital nodes − synchronizers (pulse shorters and edge detectors), and also a hysteresis node that leads to increase the stability and solve the problem of detection near-to-equal frequencies and phases.

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture

Deep neural networks have revolutionized a variety of applications in varying domains like autonomous vehicles, weather forecasting, cancer detection, surveillance, traffic management, and so on. The convolutional neural network (CNN) is the state-of-the-art technique for many machine learning tasks in the image and video processing domains. Deployment of CNNs on embedded systems with lower processing power and smaller power budget is a challenging task. Recent studies have shown the effectiveness of field-programmable gate array (FPGA) as a hardware accelerator for the CNNs that can deliver high performance at low power budgets. Majority of computations in CNNs involve 2-D convolution. Winograd minimal filtering-based algorithm is the most efficient technique for calculating convolution for smaller filter sizes. CNNs also consist of fully connected layers that are computed using general element-wise matrix multiplication (GEMM). In this article, we propose a unified architecture named UniWiG, where both Winograd-based convolution and GEMM can be accelerated using the same set of processing elements. This approach leads to efficient utilization of FPGA hardware resources while computing all layers in the CNN. The proposed architecture shows performance improvement in the range of $1.4\times $ to $4.02\times $ with only 13% additional FPGA resources with respect to the baseline GEMM-based architecture. We have mapped popular CNN models like AlexNet and VGG-16 onto the proposed accelerator and the measured performance compares favorably with other state-of-the-art implementations. We have also analyzed the vulnerability of the accelerator to the side-channel attacks. Preliminary investigations show that the UniWiG architecture is more robust to memory side-channel attacks than direct convolution-based techniques.

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs. However, it is still difficult to achieve high performance multi-task acceleration in multi-FPGA systems due to the resource contention in limited hardware resources and reconfiguration overhead. In this paper, we propose a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. At the first scheduling stage, we select an appropriate computing unit for each task considering the subtask similarity and resource requirement similarity to reduce the possibility of reconfiguration and resource contention. At the second scheduling stage, we coordinate the subtask scheduling and placement to make full use of the hardware resources of FPGAs and improve the acceleration performance. Experiments show that our two-stage scheduling approach significantly reduces the tasks makespan and improves the utilization of resources compared with other traditional methods.

A 6LoWPAN Accelerator for Internet of Things Endpoint Devices

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people, and processes interact with each other. Challenges in endpoint devices (EDs) communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This paper presents an IPv6 over low power wireless personal area networks (6LoWPAN) accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous EDs at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator.

Improved Reliability of FPGA-Based PUF Identification Generator Design

Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n -bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25°C to 70°C with ± 10% variation in the supply voltage.

Improved Architecture of FDTD Dataflow Machine for Higher Performance Electromagnetic Wave Simulation

As a portable high-performance computing technology for electromagnetic wave simulations, several kinds of dedicated computers for the finite-difference time-domain (FDTD) method have been considered. We previously proposed a dataflow architecture FDTD dedicated computer and showed that the estimated performance of the FDTD dataflow machine could exceed those of the high-end PC and GPU computers. On the other hand, the digital circuit of our previously proposed FDTD dataflow machine was inefficiently implemented in the field-programmable gate array (FPGA) owing to dual-mode operations of the normal grids and the perfectly matched layer (PML) grids, that is, almost half parts of the FPGA hardware resources were not used in our previously proposed machine. This paper proposes a modified architecture of the 3-D FDTD dedicated computer to improve the inefficient use of the FPGA hardware resources. The modified digital circuit of the FDTD scheme is designed to execute the FDTD calculation for eight normal grids or four PML grids. In the modified machine, there are almost no unused parts of hardware resources, and double size of FDTD scheme circuits can be implemented in the same size FPGA compared with the previously proposed machine.

System of a programmable-chip-based image-processing system

Recent advances in semiconductor technology have made it possible to integrate an entire system including processors, memory, and other system units into a single programmable chip [a field programmable gate array (FPGA)]. These configurations, called system on a programmable chip (SOPC), have the advantage of being designed and implemented quicker than traditional technologies and are relatively cheap to produce for low volume applications. One processor-intensive application, which is ideal for SOPC technology, is that of image processing where there is a repeated application of operations on the two-dimensional data. We present the results of research that investigate the use of SOPC technology in building a real-time image-processing system with the capability of performing video acquisition, image processing, and image display. In order to solve the complex on-chip data communication, while not degrading the transfer speed of large amounts of video data, a novel and effective bus arbitration solution called “simultaneously multimastering Avalon streaming transfer with peripheral-controlled waitrequest” is developed. Rather than using the software approach to initialize direct memory access (DMA) like transfers, this solution takes advantage of the FPGA hardware resources to perform bus arbitration and hence increase system efficiency.

Optimal utilization of available reconfigurable hardware resources

Field programmable gate arrays (FPGAs) are continuously gaining momentum and becoming essential part of today’s digital systems and applications. The growing use of these devices coupled with increasingly more complex and integrated designs necessitates search for techniques in efficient utilization of their internal resources. Standard HDL coding techniques and synthesis tools implement logic to look up table (LUT) based architecture. The resulting design utilizes more area on the chip and some fast and dedicated areas and resources of the chip remain unutilized. This in turn results in slower clock rates and larger critical path lengths, hence the design remains inefficient in terms of both speed and area. In this paper we present and discuss techniques to effectively utilize the FPGA dedicated resources in order to speed up achievable clock rates and reduce the FPGA area utilization. Various useful HDL constructs are presented that utilize dedicated hardware resources of modern Xilinx FPGAs. Optimization techniques are presented with implementation examples and corresponding quantitative performance evaluation. In most of the cases we have achieved 50% reduction in chip area utilization and simultaneously improved timing results significantly.

Area, speed and power measurements of FPGA-based complex orthogonal space-time block code channel encoders

Space-time coding (STC) is an important milestone in modern wireless communications. In this technique, more copies of the same signal are transmitted through different antennas (space) and different symbol periods (time), to improve the robustness of a wireless system by increasing its diversity gain. STCs are channel coding algorithms that can be readily implemented on a field programmable gate array (FPGA) device. This work provides some figures for the amount of required FPGA hardware resources, the speed that the algorithms can operate and the power consumption requirements of a space-time block code (STBC) encoder. Seven encoder very high-speed integrated circuit hardware description language (VHDL) designs have been coded, synthesised and tested. Each design realises a complex orthogonal space-time block code with a different transmission matrix. All VHDL designs are parameterisable in terms of sample precision. Precisions ranging from 4 bits to 32 bits have been synthesised. Alamouti's STBC encoder design [Alamouti, S.M. (1998), ‘A Simple Transmit Diversity Technique for Wireless Communications’, IEEE Journal on Selected Areas in Communications, 16:55–108.] proved to be the best trade-off, since it is on average 3.2 times smaller, 1.5 times faster and requires slightly less power than the next best trade-off in the comparison, which is a 3/4-rate full-diversity 3Tx-antenna STBC.